IEICE TRANSACTIONS on Fundamentals
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
Summary :
PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2545-2553
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2545
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
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Hiroaki KONOURA, Yukio MITSUYAMA, Masanori HASHIMOTO, Takao ONOYE, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2545-2553, December 2011, doi: 10.1587/transfun.E94.A.2545.
Abstract: PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2545/_p
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@ARTICLE{e94-a_12_2545,
author={Hiroaki KONOURA, Yukio MITSUYAMA, Masanori HASHIMOTO, Takao ONOYE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Stress Probability Computation for Estimating NBTI-Induced Delay Degradation},
year={2011},
volume={E94-A},
number={12},
pages={2545-2553},
abstract={PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.},
keywords={},
doi={10.1587/transfun.E94.A.2545},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2545
EP - 2553
AU - Hiroaki KONOURA
AU - Yukio MITSUYAMA
AU - Masanori HASHIMOTO
AU - Takao ONOYE
PY - 2011
DO - 10.1587/transfun.E94.A.2545
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error.
ER -
English
