IEICE TRANSACTIONS on Fundamentals
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Summary :
This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2693-2700
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2693
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Design
Authors
Keyword
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Shunsuke OKUMURA, Yuki KAGIYAMA, Yohei NAKATA, Shusuke YOSHIMOTO, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2693-2700, December 2011, doi: 10.1587/transfun.E94.A.2693.
Abstract: This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2693/_p
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@ARTICLE{e94-a_12_2693,
author={Shunsuke OKUMURA, Yuki KAGIYAMA, Yohei NAKATA, Shusuke YOSHIMOTO, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory},
year={2011},
volume={E94-A},
number={12},
pages={2693-2700},
abstract={This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.},
keywords={},
doi={10.1587/transfun.E94.A.2693},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2693
EP - 2700
AU - Shunsuke OKUMURA
AU - Yuki KAGIYAMA
AU - Yohei NAKATA
AU - Shusuke YOSHIMOTO
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2011
DO - 10.1587/transfun.E94.A.2693
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.
ER -
English
