IEICE TRANSACTIONS on Fundamentals
A Flexible Architecture for TURBO and LDPC Codes
Summary :
Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2392-2395
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2392
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Yun CHEN, Yuebin HUANG, Chen CHEN, Changsheng ZHOU, Xiaoyang ZENG, "A Flexible Architecture for TURBO and LDPC Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2392-2395, December 2012, doi: 10.1587/transfun.E95.A.2392.
Abstract: Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2392/_p
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@ARTICLE{e95-a_12_2392,
author={Yun CHEN, Yuebin HUANG, Chen CHEN, Changsheng ZHOU, Xiaoyang ZENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Flexible Architecture for TURBO and LDPC Codes},
year={2012},
volume={E95-A},
number={12},
pages={2392-2395},
abstract={Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.},
keywords={},
doi={10.1587/transfun.E95.A.2392},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Flexible Architecture for TURBO and LDPC Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2392
EP - 2395
AU - Yun CHEN
AU - Yuebin HUANG
AU - Chen CHEN
AU - Changsheng ZHOU
AU - Xiaoyang ZENG
PY - 2012
DO - 10.1587/transfun.E95.A.2392
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.
ER -
English
