In this letter, a novel projection algorithm is proposed in which projection onto a triangle consisting of the three even-vertices closest to the vector to be projected replaces check polytope projection, achieving the same FER performance as exact projection algorithm in both high-iteration and low-iteration regime. Simulation results show that compared with the sparse affine projection algorithm (SAPA), it can improve the FER performance by 0.2 dB as well as save average number of iterations by 4.3%.

Given an odd prime q and an integer m ≤ q, a binary mq × q2 quasi-cyclic parity-check matrix H(m, q) can be constructed for an array low-density parity-check (LDPC) code C (m, q). In this letter, we investigate the first separating redundancy of C (m, q). We prove that H (m, q) is 1-separating for any pair of (m, q), from which we conclude that the first separating redundancy of C (m, q) is upper bounded by mq. Then we show that our upper bound on the first separating redundancy of C (m, q) is tighter than the general deterministic and constructive upper bounds in the literature. For m=2, we further prove that the first separating redundancy of C (2, q) is 2q for any odd prime q. For m ≥ 3, we conjecture that the first separating redundancy of C (m, q) is mq for any fixed m and sufficiently large q.

This paper presents a novel optimization-based decoding algorithm for LDPC codes. The proposed decoding algorithm is based on a proximal gradient method for solving an approximate maximum a posteriori (MAP) decoding problem. The key idea of the proposed algorithm is the use of a code-constraint polynomial to penalize a vector far from a codeword as a regularizer in the approximate MAP objective function. A code proximal operator is naturally derived from a code-constraint polynomial. The proposed algorithm, called proximal decoding, can be described by a simple recursive formula consisting of the gradient descent step for a negative log-likelihood function corresponding to the channel conditional probability density function and the code proximal operation regarding the code-constraint polynomial. Proximal decoding is experimentally shown to be applicable to several non-trivial channel models such as LDPC-coded massive MIMO channels, correlated Gaussian noise channels, and nonlinear vector channels. In particular, in MIMO channels, proximal decoding outperforms known massive MIMO detection algorithms, such as an MMSE detector with belief propagation decoding. The simple optimization-based formulation of proximal decoding allows a way for developing novel signal processing algorithms involving LDPC codes.

The Euclidean projection operation is the most complex and time-consuming of the alternating direction method of multipliers (ADMM) decoding algorithms, resulting in a large number of resources when deployed on hardware platforms. We propose a simplified line segment projection algorithm (SLSA) and present the hardware design and the quantization scheme of the SLSA. In simulation results, the proposed SLSA module has a better performance than the original algorithm with the same fixed bitwidths due to the centrosymmetric structure of SLSA. Furthermore, the proposed SLSA module with a simpler structure without hypercube projection can reduce time consuming by up to 72.2% and reduce hardware resource usage by more than 87% compared to other Euclidean projection modules in the experiments.

This paper proposes an efficient scheduling algorithm for the layered decoding of block low-density parity-check (LDPC) codes. To efficiently configure check node-based scheduling groups, the proposed algorithm utilizes the base matrix of the block LDPC code for a block-by-block scheduling group configuration; i.e., the proposed algorithm generates a scheduling group of check nodes, satisfying the weight condition of the layered decoding, which is performed in block units (including several check nodes). Therefore, unlike the conventional scheduling algorithms performed in node units, the proposed algorithm can efficiently generate scheduling groups for layered decoding at low computational complexity and memory requirements. In addition, to accelerate the decoding convergence speed, check nodes are allocated in each scheduling group such that messages from check nodes up to the current group are delivered as evenly as possible to bit nodes. Simulation results confirm that the proposed algorithm can accelerate decoding convergence compared to other block-based scheduling algorithms for layered decoding of block LDPC codes.

In this letter, we study low-density parity-check (LDPC) codes for noisy channels with insertion and deletion (ID) errors. We first propose a design method of irregular LDPC codes for such channels, which can be used to simultaneously obtain degree distributions for different noise levels. We then show the asymptotic/finite-length decoding performances of designed codes and compare them with the symmetric information rates of cascaded ID-noisy channels. Moreover, we examine the relationship between decoding performance and a code structure of irregular LDPC codes.

Accumulate Repeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.

A properly designed stopping criterion for iterative decoding algorithms can save a number of iterations and lead to a considerable reduction of system latency. The symbol flipping decoding algorithms based on prediction (SFDP) have been proposed recently for efficient decoding of non-binary low-density parity-check (LDPC) codes. To detect the decoding frames with slow convergence or even non-convergence, we track the number of oscillations on the value of objective function during the iterations. Based on this tracking number, we design a simple stopping criterion for the SFDP algorithms. Simulation results show that the proposed stopping criterion can significantly reduce the number of iterations at low signal-to-noise ratio regions with slight error performance degradation.

This paper presents the bit error rate (BER) performance of frequency domain equalization (FDE) using cyclic-shifted code division multiplexing (CDM) pilot signals for single-carrier line-of-sight (LOS) - multiple-input multiple-output (MIMO) multiplexing. We propose applying different cyclic-shift resources of the same Zadoff-Chu sequence to transmission-stream-specific pilot signals that are essential for estimating the channel response for FDE and phase noise in LOS-MIMO. To validate the effectiveness of the cyclic-shifted pilot multiplexing, we use partial low-density parity-check (LDPC) coding with double Gray mapping and collaborative decoding. Simulations show that pilot signal multiplexing using a cyclic-shifted Zadoff-Chu sequence, and frequency domain averaging of the estimated channel response are effective in achieving accurate channel estimation for single-carrier LOS-MIMO. We also show that the required received signal-to-noise power ratio at the BER of 10-7 using partial LDPC coding is decreased by more than 6.6dB compared to that without LDPC coding even for the deep notch depth of -20dB regardless of the relationship between the notch frequencies in the direct and cross links for 2×2 LOS-MIMO in a Rummler fading channel. Therefore, we conclude that the CDM-based pilot signal multiplexing with different cyclic shifts is effective in accurately estimating the channel response specific to the combination sets of transmitter and receiver antennas and in achieving a low pilot-overhead loss for single-carrier LOS-MIMO.

We propose a coding/decoding strategy that surpasses the symmetric information rate of a binary insertion/deletion (ID) channel and approaches the Markov capacity of the channel. The proposed codes comprise inner trellis codes and outer irregular low-density parity-check (LDPC) codes. The trellis codes are designed to mimic the transition probabilities of a Markov input process that achieves a high information rate, whereas the LDPC codes are designed to maximize an iterative decoding threshold in the superchannel (concatenation of the ID channels and trellis codes).

For insertion and deletion channels, there are many coding schemes based on low-density parity-check (LDPC) codes, such as spatially coupled (SC) LDPC codes and concatenated codes of irregular LDPC codes and markers. However, most of the previous works have problems, such as poor finite-length performance and unrealistic settings for codeword lengths and decoding iterations. Moreover, when using markers, the decoder receives log-likelihood (LLR) messages with different statistics depending on code bit position. In this paper, we propose a novel concatenation scheme using protograph-based LDPC code and markers that offers excellent asymptotic/finite-length performance and a structure that controls the irregularity of LLR messages. We also present a density evolution analysis and a simple optimization procedure for the proposed concatenated coding scheme. For two decoding scenarios involving decoding complexity, both asymptotic decoding thresholds and finite-length performance demonstrate that the newly designed concatenated coding scheme outperforms the existing counterparts: the irregular LDPC code with markers, the SC-LDPC code, and the protograph LDPC code, which is optimized for an additive white Gaussian noise channel, with markers.

In this letter, the structural analysis of nonbinary cyclic and quasi-cyclic (QC) low-density parity-check (LDPC) codes with α-multiplied parity-check matrices (PCMs) is concerned. Using analytical methods, several structural parameters of nonbinary cyclic and QC LDPC codes with α-multiplied PCMs are determined. In particular, some classes of nonbinary LDPC codes constructed from finite fields and finite geometries are shown to have good minimum and stopping distances properties, which may explain to some extent their wonderful decoding performances.

Over the past two decades, irregular low-density parity-check (LDPC) codes have not been able to decode information corrupted by insertion and deletion (ID) errors without markers. In this paper, we bring to light the existence of irregular LDPC codes that approach the symmetric information rates (SIR) of the channel with ID errors, even without markers. These codes have peculiar shapes in their check-node degree distributions. Specifically, the check-node degrees are scattered and there are degree-2 check nodes. We propose a code construction method based on the progressive edge-growth algorithm tailored for the scattered check-node degree distributions, which enables the SIR-approaching codes to progress in the finite-length regime. Moreover, the SIR-approaching codes demonstrate asymptotic and finite-length performance that outperform the existing counterparts, namely, concatenated coding of irregular LDPC codes with markers and spatially coupled LDPC codes.

4K/8K satellite broadcasting featuring ultra-high definition video and sound was launched in Japan in 2018. This is the first 8K ultra high definition television (UHDTV) broadcasting in the world, with 16 times as many pixels as HDTV and 3D sound with 22.2ch audio. The large amount of information that has to be transmitted means that a new satellite broadcasting transmission system had to be developed. In this paper, we describe this transmission system, focusing on the technology that enables 4K/8K UHDTV satellite broadcasting.

We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.

Low-density parity-check (LDPC) codes can be used to improve the storage reliability of multi-level cell (MLC) flash memories because of their strong error-correcting capability. In order to improve the weighted bit-flipping (WBF) decoding of LDPC codes in MLC flash memories with cell-to-cell interference (CCI), we propose two strategies of normalizing weights and adjusting log-likelihood ratio (LLR) values. Simulation results show that the WBF decoding under the proposed strategies is much advantageous in both error and convergence performances over existing WBF decoding algorithms. Based on complexity analysis, the strategies provide the WBF decoding with a good tradeoff between performance and complexity.

In racetrack memories (RM), a position error (insertion or deletion error) results from unstable data reading. For position errors in RM with multiple read-heads (RHs), we propose a protograph-based LDPC coded system specified by a protograph and a protograph-aware permutation. The protograph-aware permutation facilitates the design and analysis of the coded system. By solving a multi-objective optimization problem, the coded system attains the properties of fast convergence decoding, a good decoding threshold, and a linear minimum distance growth. In addition, the coded system can adapt to varying numbers of RHs without any modification. The asymptotic decoding thresholds with a limited number of iterations verify the good properties of the system. Furthermore, for varying numbers of RHs, the simulation results with both small and large number of iterations, exhibit excellent decoding performances, both with short and long block lengths, and without error floors.

In fifth-generation mobile communications systems (5G), grant-free non-orthogonal multiple access (NOMA) schemes have been considered as a way to accommodate the many wireless connections required for Internet of Things (IoT) devices. In NOMA schemes, both system capacity enhancement and transmission protocol simplification are achieved, and an overload test of more than one hundred percent of the transmission samples over conducted. Multi-user shared multiple access (MUSA) has been proposed as a representative scheme for NOMA. However, the performance of MUSA has not been fully analyzed nor compared to other NOMA or orthogonal multiple access schemes. Therefore, in this study, we theoretically and numerically analyze the performance of MUSA in uplink fading environments and compare it with orthogonal frequency division multiple access (OFDMA), space division multiple access-based OFDMA, low-density signature, and sparse code multiple access. The characteristics and superiority of MUSA are then clarified.

This paper proposed an iterative soft interference canceller (IC) referred to as turbo equalizer for the self-coherent detection, and extrinsic information transfer (EXIT) chart based irregular low density parity check (LDPC) code optimization for the turbo equalizer in optical fiber short-reach transmissions. The self-coherent detection system is capable of linear demodulation by a single photodiode receiver. However, the self-coherent detection suffers from the interference induced by signal-signal beat components, and the suppression of the interference is a vital goal of self-coherent detection. For improving the error-free signal detection performance of the self-coherent detection, we proposed an iterative soft IC with the aid of forward error correction (FEC) decoder. Furthermore, typical FEC code is no longer appropriate for the iterative detection of the turbo equalizer. Therefore, we designed an appropriate LDPC code by using EXIT chart aided code design. The validity of the proposed turbo equalizer with the appropriate LDPC is confirmed by computer simulations.

The symbol flipping decoding algorithms based on prediction (SFDP) for non-binary LDPC codes perform well in terms of error performances but converge slowly when compared to other symbol flipping decoding algorithms. In order to improve the convergence rate, we design new flipping rules with two phases for the SFDP algorithms. In the first phase, two or more symbols are flipped at each iteration to allow a quick increase of the objective function. While in the second phase, only one symbol is flipped to avoid the oscillation of the decoder when the objective function is close to its maximum. Simulation results show that the SFDP algorithms with the proposed flipping rules can reduce the average number of iterations significantly, whereas having similar performances when compared to the original SFDP algorithms.