A novel self-synchronizable decoding algorithm for transmissions with redundant information is proposed. We assume that desynchronization occurs because a continuous deletion of bits in the channel. The decoder bases its decision on a metric which involves the syndrome and the Hamming distance between certain codeword and its corresponding updated codeword after one iteration of sum-product decoding. The foundation of the previous assumption relies on what we called "CP-distance." The larger the CP-distance of a code the better the synchronization characteristics. Moreover, our proposal is not restricted to cyclically permutable (CP) codes as previous proposals. Theoretical foundation and experimental results show good performance of our algorithm.

In this paper, a modified Belief Propagation (BP) decoding algorithm for low-density parity check (LDPC) codes based on minimum mean square error (MMSE) criterion is proposed. This modified algorithm uses linear equation to replace the hyperbolic function in the original BP algorithm and optimizes the linear approximation error based on MMSE criterion. As a result, compared with the standard BP algorithm the computational complexity is reduced significantly as the modified algorithm requires only addition operations to implement. Besides that simulation results show our modified algorithm can achieve an error performance very close to the BP algorithm on the additive white Gaussian noise channel.

This letter presents an approach to the construction of multiple-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes based on hyperplanes (µ-flats) of two different dimensions in Euclidean geometries. The codes constructed with this method have the same code length, multiple-rate and large stopping sets while maintaining the same basic hardware architecture. The code performance is investigated in terms of the bit error rate (BER) and compared with those of the LDPC codes which are proposed in IEEE 802.16e standard. Simulation results show that our codes perform very well and have low error floors over the AWGN channel.

Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.

In this paper, we investigate the smallest value of p for which a (J,L,p)-QC LDPC code with girth 6 exists for J=3 and J=4. For J=3, we determine the smallest value of p for any L. For J=4, we determine the smallest value of p for L ≤ 301. Furthermore we provide examples of specific constructions meeting these smallest values of p.

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

We newly design time-varying low-density parity-check convolutional codes (LDPC-CCs) based on parity check polynomials of the convolutional codes with a time period of 3, and show that BER (Bit Error Rate) performance in the time-varying LDPC-CCs with a time period of 3 is better than that in the conventional time-varying LDPC-CCs with a time period of 2 in the same coding rate with the nearly equal constraint length.

This paper proposes a parallelized DVC framework that treats each bitplane independently to reduce the decoding time. Unfortunately, simple parallelization generates inaccurate bit probabilities because additional side information is not available for the decoding of subsequent bitplanes, which degrades encoding efficiency. Our solution is an effective estimation method that can calculate the bit probability as accurately as possible by index assignment without recourse to side information. Moreover, we improve the coding performance of Rate-Adaptive LDPC (RA-LDPC), which is used in the parallelized DVC framework. This proposal selects a fitting sparse matrix for each bitplane according to the syndrome rate estimation results at the encoder side. Simulations show that our parallelization method reduces the decoding time by up to 35[%] and achieves a bit rate reduction of about 10[%].

This paper clarifies the adequacy of the linear channel coding approach for Slepian-Wolf coding of individual sequences. A sufficient condition for ensembles of linear codes from which a universal Slepian-Wolf code can be constructed is given. Our result reveals that an ensemble of LDPC codes gives a universal code for Slepian-Wolf coding of individual sequences.

Generalized quasi-cyclic (GQC) codes form a wide and useful class of linear codes that includes thoroughly quasi-cyclic codes, finite geometry (FG) low density parity check (LDPC) codes, and Hermitian codes. Although it is known that the systematic encoding of GQC codes is equivalent to the division algorithm in the theory of Grobner basis of modules, there has been no algorithm that computes Grobner basis for all types of GQC codes. In this paper, we propose two algorithms to compute Grobner basis for GQC codes from their parity check matrices; we call them echelon canonical form algorithm and transpose algorithm. Both algorithms require sufficiently small number of finite-field operations with the order of the third power of code-length. Each algorithm has its own characteristic. The first algorithm is composed of elementary methods and is appropriate for low-rate codes. The second algorithm is based on a novel formula and has smaller computational complexity than the first one for high-rate codes with the number of orbits (cyclic parts) less than half of the code length. Moreover, we show that a serial-in serial-out encoder architecture for FG LDPC codes is composed of linear feedback shift registers with the size of the linear order of code-length; to encode a binary codeword of length n, it takes less than 2n adder and 2n memory elements.

In this letter, we analyze the convergence speed of layered decoding of block-type low-density parity-check codes and verify that the layered decoding gives faster convergence speed than the sequential decoding with randomly selected check node subsets. Also, it is shown that using more subsets than the maximum variable node degree does not improve the convergence speed.

Low-density parity-check (LDPC) codes are linear block codes defined by sparse parity-check matrices. The codes exhibit excellent performance under iterative decoding, and the weight distribution is used to analyze lower error probability of their decoding performance. In this paper, we propose a probabilistic method for computing the weight distribution of LDPC codes. The proposed method efficiently finds low-weight codewords in a given LDPC code by using Stern's algorithm, and stochastically computes the low part of the weight distribution from the frequency of the found codewords. It is based on a relation between the number of codewords with a given weight and the rate of generating the codewords in Stern's algorithm. In the numerical results for LDPC codes of length 504, 1008 and 4896, we could compute the weight distribution by the proposed method with greater accuracy than by conventional methods.

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

In this paper, we introduce layered low-density generator matrix (Layered-LDGM) codes for super high definition (SHD) scalable video systems. The layered-LDGM codes maintain the correspondence relationship of each layer from the encoder side to the decoder side. This resulting structure supports partial decoding. Furthermore, the proposed layered-LDGM codes create highly efficient forward error correcting (FEC) data by considering the relationship between each scalable component. Therefore, the proposed layered-LDGM codes raise the probability of restoring the important components. Simulations show that the proposed layered-LDGM codes offer better error resiliency than the existing method which creates FEC data for each scalable component independently. The proposed layered-LDGM codes support partial decoding and raise the probability of restoring the base component. These characteristics are very suitable for scalable video coding systems.

Multi-carrier code division multiple access (MC-CDMA) is a promising wireless access technique for the next generation mobile communications systems, in which broadband packet data services will dominate. Hybrid automatic repeat request (HARQ) is an indispensable error control technique for high quality packet data transmission. The HARQ throughput performance of multi-code MC-CDMA degrades due to the presence of residual inter-code interference (ICI) after frequency-domain equalization (FDE). To reduce the residual ICI and improve the throughput performance, a frequency-domain soft interference cancellation (FDSIC) technique can be applied. An important issue is the generation of accurate residual ICI replica for FDSIC. In this paper, low-density parity-check coded (LDPC-coded) MC-CDMA HARQ is considered. We generate the residual ICI replica from a-posteriori log-likelihood ratio (LLR) of LDPC decoder output and evaluate, by computer simulation, the throughput performance in a frequency-selective Rayleigh fading channel. We show that if the residual ICI is removed, MC-CDMA can provide a throughput performance superior to orthogonal frequency division multiplexing (OFDM).

The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.11n standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

In this paper, we analyze the robustness for low-density parity-check (LDPC) codes over the Gilbert-Elliott (GE) channel. For this purpose we propose a density evolution method for the case where LDPC decoder uses the mismatched parameters for the GE channel. Using this method, we derive the region of tuples of true parameters and mismatched decoding parameters for the GE channel, where the decoding error probability approaches asymptotically to zero.

In this paper, we propose a method to ensure larger number of channels than the current Satellite Digital Multimedia Broadcasting (S-DMB). For Backwards Compatibility (BC) for legacy subscribers, we apply Hierarchical Eight Phase Shift Keying (H-8PSK) modulation and Low Density Parity Check (LDPC) code. Using the newly proposed method, we simulate the performance deterioration of the existing stream and the performance of the new stream according to code rates of LDPC and deviation angle. As the result, we present the optimal deviation angle, which produces the least performance deterioration of the existing system and the best performance of the new system, drawing satisfiable improvement in transmission rate.

This paper presents an improved min-sum iterative decoding scheme for regular and irregular LDPC codes. The proposed decoding scheme scales the extrinsic soft information from variable nodes to check. Different scaling factors are applied for iterations and the scaling factors are obtained by a simplified vector optimization method.