IEICE TRANSACTIONS on Fundamentals
Structured Analog Circuit and Layout Design with Transistor Array
Summary :
This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2475-2486
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2475
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Level Design
Authors
Bo YANG
Design Algorithm Laboratory, Inc.
Qing DONG
The University of Kitakyushu
Jing LI
Design Algorithm Laboratory, Inc.
Shigetoshi NAKATAKE
The University of Kitakyushu
Keyword
Latest Issue
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Bo YANG, Qing DONG, Jing LI, Shigetoshi NAKATAKE, "Structured Analog Circuit and Layout Design with Transistor Array" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2475-2486, December 2013, doi: 10.1587/transfun.E96.A.2475.
Abstract: This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2475/_p
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@ARTICLE{e96-a_12_2475,
author={Bo YANG, Qing DONG, Jing LI, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Structured Analog Circuit and Layout Design with Transistor Array},
year={2013},
volume={E96-A},
number={12},
pages={2475-2486},
abstract={This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.},
keywords={},
doi={10.1587/transfun.E96.A.2475},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Structured Analog Circuit and Layout Design with Transistor Array
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2475
EP - 2486
AU - Bo YANG
AU - Qing DONG
AU - Jing LI
AU - Shigetoshi NAKATAKE
PY - 2013
DO - 10.1587/transfun.E96.A.2475
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.
ER -
English
