IEICE TRANSACTIONS on Fundamentals
Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path
Summary :
A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.2 pp.606-615
- Publication Date
- 2014/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.606
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Ittetsu TANIGUCHI
Ritsumeikan University
Kohei AOKI
Ritsumeikan University
Hiroyuki TOMIYAMA
Ritsumeikan University
Praveen RAGHAVAN
IMEC
Francky CATTHOOR
IMEC,Katholieke Universiteit Leuven
Masahiro FUKUI
Ritsumeikan University
Keyword
Latest Issue
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Ittetsu TANIGUCHI, Kohei AOKI, Hiroyuki TOMIYAMA, Praveen RAGHAVAN, Francky CATTHOOR, Masahiro FUKUI, "Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 2, pp. 606-615, February 2014, doi: 10.1587/transfun.E97.A.606.
Abstract: A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.606/_p
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@ARTICLE{e97-a_2_606,
author={Ittetsu TANIGUCHI, Kohei AOKI, Hiroyuki TOMIYAMA, Praveen RAGHAVAN, Francky CATTHOOR, Masahiro FUKUI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path},
year={2014},
volume={E97-A},
number={2},
pages={606-615},
abstract={A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.},
keywords={},
doi={10.1587/transfun.E97.A.606},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 606
EP - 615
AU - Ittetsu TANIGUCHI
AU - Kohei AOKI
AU - Hiroyuki TOMIYAMA
AU - Praveen RAGHAVAN
AU - Francky CATTHOOR
AU - Masahiro FUKUI
PY - 2014
DO - 10.1587/transfun.E97.A.606
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2014
AB - A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.
ER -
English
