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[Author] Francky CATTHOOR(4hit)

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  • Thermal-Comfort Aware Online Co-Scheduling Framework for HVAC, Battery Systems, and Appliances in Smart Buildings

    Daichi WATARI  Ittetsu TANIGUCHI  Francky CATTHOOR  Charalampos MARANTOS  Kostas SIOZIOS  Elham SHIRAZI  Dimitrios SOUDRIS  Takao ONOYE  

     
    INVITED PAPER

      Pubricized:
    2022/10/24
      Vol:
    E106-A No:5
      Page(s):
    698-706

    Energy management in buildings is vital for reducing electricity costs and maximizing the comfort of occupants. Excess solar generation can be used by combining a battery storage system and a heating, ventilation, and air-conditioning (HVAC) system so that occupants feel comfortable. Despite several studies on the scheduling of appliances, batteries, and HVAC, comprehensive and time scalable approaches are required that integrate such predictive information as renewable generation and thermal comfort. In this paper, we propose an thermal-comfort aware online co-scheduling framework that incorporates optimal energy scheduling and a prediction model of PV generation and thermal comfort with the model predictive control (MPC) approach. We introduce a photovoltaic (PV) energy nowcasting and thermal-comfort-estimation model that provides useful information for optimization. The energy management problem is formulated as three coordinated optimization problems that cover fast and slow time-scales by considering predicted information. This approach reduces the time complexity without a significant negative impact on the result's global nature and its quality. Experimental results show that our proposed framework achieves optimal energy management that takes into account the trade-off between electricity expenses and thermal comfort. Our sensitivity analysis indicates that introducing a battery significantly improves the trade-off relationship.

  • Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling

    Yuki KOBAYASHI  Murali JAYAPALA  Praveen RAGHAVAN  Francky CATTHOOR  Masaharu IMAI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E91-A No:2
      Page(s):
    604-612

    Clustering L0 buffers is effective for energy reduction in the instruction memory caches of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. For improving the energy efficiency of L0 clusters, an operation shuffling is proposed, which explores assignment of operations for each cycle, generates various schedules, and evaluates them to find an energy efficient schedule. This approach can find energy efficient schedules, however, it takes a long time to obtain the final result. In this paper, we propose a new method to directly generate an energy efficient schedule without iterations of operation shuffling. In the proposed method, a compiler schedules operations using the result of the single operation shuffling as a constraint. We propose some optimization algorithms to generate an energy efficient schedule for a given L0 cluster organization. The proposed method can drastically reduce the computational effort since it performs the operation shuffling only once. The experimental results show that comparable energy reduction is achieved by using the proposed method while the computational effort can be reduced significantly over the conventional operation shuffling.

  • Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path

    Ittetsu TANIGUCHI  Kohei AOKI  Hiroyuki TOMIYAMA  Praveen RAGHAVAN  Francky CATTHOOR  Masahiro FUKUI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E97-A No:2
      Page(s):
    606-615

    A fast and accurate architecture exploration for high performance and low energy VLIW data-path is proposed. The main contribution is a method to find Pareto optimal FU structures, i.e., the optimal number of FUs and the best instruction assignment for each FU. The proposed architecture exploration method is based on GA and enables the effective exploration of vast solution space. Experimental results showed that proposed method was able to achieve fast and accurate architecture exploration. For most cases, the estimation error was less than 1%.

  • Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors

    Ittetsu TANIGUCHI  Praveen RAGHAVAN  Murali JAYAPALA  Francky CATTHOOR  Yoshinori TAKEUCHI  Masaharu IMAI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E92-A No:4
      Page(s):
    1161-1173

    Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.