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Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors

Ittetsu TANIGUCHI, Praveen RAGHAVAN, Murali JAYAPALA, Francky CATTHOOR, Yoshinori TAKEUCHI, Masaharu IMAI

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Summary :

Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.4 pp.1161-1173
Publication Date
2009/04/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E92.A.1161
Type of Manuscript
PAPER
Category
VLSI Design Technology and CAD

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