Low-Power Motion Estimation Processor with 3D Stacked Memory

Shuping ZHANG; Jinjia ZHOU; Dajiang ZHOU; Shinji KIMURA; Satoshi GOTO

doi:10.1587/transfun.E98.A.1431

IEICE TRANSACTIONS on Fundamentals

Low-Power Motion Estimation Processor with 3D Stacked Memory

Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO

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Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1431-1441

Publication Date: 2015/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.1431

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Shuping ZHANG
  Waseda University
Jinjia ZHOU
  Waseda University
Dajiang ZHOU
  Waseda University
Shinji KIMURA
  Waseda University
Satoshi GOTO
  Waseda University

Keyword

3DIC design, motion estimation processor, low power design, memory stacking

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Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO, "Low-Power Motion Estimation Processor with 3D Stacked Memory" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 7, pp. 1431-1441, July 2015, doi: 10.1587/transfun.E98.A.1431.
Abstract: Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1431/_p

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@ARTICLE{e98-a_7_1431,
author={Shuping ZHANG, Jinjia ZHOU, Dajiang ZHOU, Shinji KIMURA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Power Motion Estimation Processor with 3D Stacked Memory},
year={2015},
volume={E98-A},
number={7},
pages={1431-1441},
abstract={Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.},
keywords={},
doi={10.1587/transfun.E98.A.1431},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - Low-Power Motion Estimation Processor with 3D Stacked Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1431
EP - 1441
AU - Shuping ZHANG
AU - Jinjia ZHOU
AU - Dajiang ZHOU
AU - Shinji KIMURA
AU - Satoshi GOTO
PY - 2015
DO - 10.1587/transfun.E98.A.1431
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.
ER -

IEICE TRANSACTIONS on Fundamentals