IEICE TRANSACTIONS on Fundamentals
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability
Summary :
As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aging-induced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1400-1409
- Publication Date
- 2016/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.1400
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Song BIAN
Kyoto University
Michihiro SHINTANI
Kyoto University
Masayuki HIROMOTO
Kyoto University
Takashi SATO
Kyoto University
Keyword
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Song BIAN, Michihiro SHINTANI, Masayuki HIROMOTO, Takashi SATO, "Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 7, pp. 1400-1409, July 2016, doi: 10.1587/transfun.E99.A.1400.
Abstract: As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aging-induced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1400/_p
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@ARTICLE{e99-a_7_1400,
author={Song BIAN, Michihiro SHINTANI, Masayuki HIROMOTO, Takashi SATO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability},
year={2016},
volume={E99-A},
number={7},
pages={1400-1409},
abstract={As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aging-induced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.},
keywords={},
doi={10.1587/transfun.E99.A.1400},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1400
EP - 1409
AU - Song BIAN
AU - Michihiro SHINTANI
AU - Masayuki HIROMOTO
AU - Takashi SATO
PY - 2016
DO - 10.1587/transfun.E99.A.1400
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aging-induced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.
ER -
English
