IEICE TRANSACTIONS on Information
Latency-Aware Bus Arbitration for Real-Time Embedded Systems
Summary :
We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.3 pp.676-679
- Publication Date
- 2007/03/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e90-d.3.676
- Type of Manuscript
- LETTER
- Category
- VLSI Systems
Authors
Keyword
Latest Issue
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Minje JUN, Kwanhu BANG, Hyuk-Jun LEE, Eui-Young CHUNG, "Latency-Aware Bus Arbitration for Real-Time Embedded Systems" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 3, pp. 676-679, March 2007, doi: 10.1093/ietisy/e90-d.3.676.
Abstract: We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.3.676/_p
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@ARTICLE{e90-d_3_676,
author={Minje JUN, Kwanhu BANG, Hyuk-Jun LEE, Eui-Young CHUNG, },
journal={IEICE TRANSACTIONS on Information},
title={Latency-Aware Bus Arbitration for Real-Time Embedded Systems},
year={2007},
volume={E90-D},
number={3},
pages={676-679},
abstract={We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.},
keywords={},
doi={10.1093/ietisy/e90-d.3.676},
ISSN={1745-1361},
month={March},}
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TY - JOUR
TI - Latency-Aware Bus Arbitration for Real-Time Embedded Systems
T2 - IEICE TRANSACTIONS on Information
SP - 676
EP - 679
AU - Minje JUN
AU - Kwanhu BANG
AU - Hyuk-Jun LEE
AU - Eui-Young CHUNG
PY - 2007
DO - 10.1093/ietisy/e90-d.3.676
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2007
AB - We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.
ER -
English
