IEICE TRANSACTIONS on Information
Scheduling Power-Constrained Tests through the SoC Functional Bus
Summary :
This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.3 pp.736-746
- Publication Date
- 2008/03/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.3.736
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSIs)
- Category
- High-Level Testing
Authors
LUKeyword
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Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Alex ORAILOLU, Hideo FUJIWARA, "Scheduling Power-Constrained Tests through the SoC Functional Bus" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 3, pp. 736-746, March 2008, doi: 10.1093/ietisy/e91-d.3.736.
Abstract: This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.3.736/_p
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@ARTICLE{e91-d_3_736,
author={Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Alex ORAILOLU, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Scheduling Power-Constrained Tests through the SoC Functional Bus},
year={2008},
volume={E91-D},
number={3},
pages={736-746},
abstract={This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.},
keywords={},
doi={10.1093/ietisy/e91-d.3.736},
ISSN={1745-1361},
month={March},}
Copy
TY - JOUR
TI - Scheduling Power-Constrained Tests through the SoC Functional Bus
T2 - IEICE TRANSACTIONS on Information
SP - 736
EP - 746
AU - Fawnizu Azmadi HUSSIN
AU - Tomokazu YONEDA
AU - Alex ORAILOLU
AU - Hideo FUJIWARA
PY - 2008
DO - 10.1093/ietisy/e91-d.3.736
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2008
AB - This paper proposes a test methodology for core-based testing of System-on-Chips by utilizing the functional bus as a test access mechanism. The functional bus is used as a transportation channel for the test stimuli and responses from a tester to the cores under test (CUT). To enable test concurrency, local test buffers are added to all CUTs. In order to limit the buffer area overhead while minimizing the test application time, we propose a packet-based scheduling algorithm called PAcket Set Scheduling (PASS), which finds the complete packet delivery schedule under a given power constraint. The utilization of test packets, consisting of a small number of bits of test data, for test data delivery allow an efficient sharing of bus bandwidth with the help of an effective buffer-based test architecture. The experimental results show that the methodology is highly effective, especially for smaller bus widths, compared to previous approaches that do not use the functional bus.
ER -
English
