IEICE TRANSACTIONS on Information
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Summary :
This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.3 pp.747-755
- Publication Date
- 2008/03/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.3.747
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSIs)
- Category
- High-Level Testing
Authors
Keyword
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Tomokazu YONEDA, Kimihiko MASUDA, Hideo FUJIWARA, "Test Scheduling for Multi-Clock Domain SoCs under Power Constraint" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 3, pp. 747-755, March 2008, doi: 10.1093/ietisy/e91-d.3.747.
Abstract: This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.3.747/_p
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@ARTICLE{e91-d_3_747,
author={Tomokazu YONEDA, Kimihiko MASUDA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Test Scheduling for Multi-Clock Domain SoCs under Power Constraint},
year={2008},
volume={E91-D},
number={3},
pages={747-755},
abstract={This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.},
keywords={},
doi={10.1093/ietisy/e91-d.3.747},
ISSN={1745-1361},
month={March},}
Copy
TY - JOUR
TI - Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
T2 - IEICE TRANSACTIONS on Information
SP - 747
EP - 755
AU - Tomokazu YONEDA
AU - Kimihiko MASUDA
AU - Hideo FUJIWARA
PY - 2008
DO - 10.1093/ietisy/e91-d.3.747
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2008
AB - This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.
ER -
English
