Synthesis of Testable Sequential Circuits with Reduced Checking Sequences

Satoshi SHIBATANI, Kozo KINOSHITA

Summary :

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

• Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.7 pp.739-746
• Publication Date: 1993/07/25
• Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design)

Authors

Satoshi SHIBATANI
Kozo KINOSHITA

Keyword

sequential circuit,  design for testability,  automated logic synthesis,  checking sequence,  state assignment