REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques

Miyako TANDAI; Takao SHINSHA; Takao NISHIDA; Kaoru MORIWAKI

REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques

Miyako TANDAI, Takao SHINSHA, Takao NISHIDA, Kaoru MORIWAKI

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This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N²-V.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.7 pp.776-790

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design)

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Miyako TANDAI, Takao SHINSHA, Takao NISHIDA, Kaoru MORIWAKI, "REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 7, pp. 776-790, July 1993, doi: .
Abstract: This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N²-V.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_7_776/_p

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@ARTICLE{e76-d_7_776,
author={Miyako TANDAI, Takao SHINSHA, Takao NISHIDA, Kaoru MORIWAKI, },
journal={IEICE TRANSACTIONS on Information},
title={REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques},
year={1993},
volume={E76-D},
number={7},
pages={776-790},
abstract={This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N²-V.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques
T2 - IEICE TRANSACTIONS on Information
SP - 776
EP - 790
AU - Miyako TANDAI
AU - Takao SHINSHA
AU - Takao NISHIDA
AU - Kaoru MORIWAKI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1993
AB - This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N²-V.
ER -