Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

Reseeding technique is proposed to improve the fault coverage in pseudo-random testing. However most of previous works on reseeding is based on storing the seeds in an external tester or in a ROM. In this paper we present a built-in reseeding technique for LFSR-based test pattern generation. The proposed structure can run both in pseudorandom mode and in reseeding mode. Besides, our method requires no storage for the seeds since in reseeding mode the seeds can be generated automatically in hardware. In this paper we also propose an efficient grouping algorithm based on simulated annealing to optimize test vector grouping. Experimental results for benchmark circuits indicate the superiority of our technique against other reseeding methods with respect to test length and area overhead. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other techniques proposed so far.

To accomplish an efficient test pattern generation, the isomorphism identification algorithm and the pseudo dominator identification algorithm are developed which are used to identify redundant faults efficiently. Results show that test pattern generation using these algorithms is very efficient.

Any minimum test set (MLTS) for locally exhaustive testing of multiple output combinational circuits (CUTs) has at least 2w test patterns, where w is the maximum number of inputs on which any output depends. In the previous researches, it is clarified that every CUT with up to four outputs has an MLTS with 2w elements. On the other hand, it can be easily shown that every CUT with more than five outputs does not have such an MLTS. It has not been however known whether every CUT with five outputs has such an MLTS or not. In this paper, it is clarified that every CUT with five outputs has such an MLTS. First, some terminologies are introduced as preliminaries. Second, features of 5(w1) dependence matrices of CUTs with five outputs and (w1) inputs are discussed. Third, an equivalence relation between dependence matrices of two CUTs is introduced. The relation means that if it holds and one of the CUTs has an MLTS with 2w elements, then the other CUT also has such an MLTS. Based on the features described above, a theorem is established that there exists a 5w dependence matrix which is equivalent to each of the above 5(w1) matrices. Finally, it is proved by the use of the theorem that every CUT with five outputs has an MLTS with 2 w elements.

In this paper, an exact algorithm for finding minimum test set which detects all testable stuck-at faults of a given combinational circit is presented. So far several heuristic algorithms for this problem are proposed, but no efficient exact algorithms are known. To solve this exactly, minimum test set problem is formalized as a minimum set covering problem, and then implicit manipulation technique using binary decision diagrams(BDDs) is applied. The algorithm presented in the paper has two contributions. One is utilization of maximal compatible fault set, which can drastically reduce the number of candidates for minimum test set. A new BDD based algorithm for extracting all maximal compatible fault sets is shown. The other is a new implicit manipulation technique handling with huge covering matrix. Actually, the algorithm using this technique can handle minimum set covrering problem with over ten thousand columns in a few minutes. Experiments using ISCAS benchmark circuits show that the algorithm is quite efficient for small(100-300 gates) circuits. A computational complexith of minimum test set problen is much higher than that of ordinary test pattern generation problem, so that practical signifcance of this method is not high. But the algorithm is still useful for evaluation of other heuristic algorithms. furthermore, this implicit manipulation technique can also be applied to other minimumset covering problems.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.

The locally exhaustive testing of multiple output combinational circuits is the test which provides exhaustive test patterns for each set of inputs on which each output depends. First, this paper presents a sufficient condition under which a minimum test set (MLTS) for the locally exhaustive testing has 2w test patterns, where w is the maximum number of inputs on which any output depends. Next, we clarify that any CUT with up to four outputs satisfies the condition, independently of w and n, where n is the number of inputs of the CUT. Finally, we clarify that any CUT with five outputs also satisfies the condition for 1w2 or n2wn.