IEICE TRANSACTIONS on Information
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
Summary :
In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.1 pp.10-16
- Publication Date
- 2010/01/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.10
- Type of Manuscript
- Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
- Category
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Hiroyuki YOTSUYANAGI, Masayuki YAMAMOTO, Masaki HASHIZUME, "Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 1, pp. 10-16, January 2010, doi: 10.1587/transinf.E93.D.10.
Abstract: In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.10/_p
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@ARTICLE{e93-d_1_10,
author={Hiroyuki YOTSUYANAGI, Masayuki YAMAMOTO, Masaki HASHIZUME, },
journal={IEICE TRANSACTIONS on Information},
title={Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops},
year={2010},
volume={E93-D},
number={1},
pages={10-16},
abstract={In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.},
keywords={},
doi={10.1587/transinf.E93.D.10},
ISSN={1745-1361},
month={January},}
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TY - JOUR
TI - Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
T2 - IEICE TRANSACTIONS on Information
SP - 10
EP - 16
AU - Hiroyuki YOTSUYANAGI
AU - Masayuki YAMAMOTO
AU - Masaki HASHIZUME
PY - 2010
DO - 10.1587/transinf.E93.D.10
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2010
AB - In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.
ER -
English
