Linking Register-Transfer and Physical Levels of Design

Fadi J. KURDAHI; Daniel D. GAJSKI; Champaka RAMACHANDRAN; Viraphol CHAIYAKUL

Linking Register-Transfer and Physical Levels of Design

Fadi J. KURDAHI, Daniel D. GAJSKI, Champaka RAMACHANDRAN, Viraphol CHAIYAKUL

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System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.9 pp.991-1005

Publication Date: 1993/09/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: High-Level Design

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Fadi J. KURDAHI, Daniel D. GAJSKI, Champaka RAMACHANDRAN, Viraphol CHAIYAKUL, "Linking Register-Transfer and Physical Levels of Design" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 9, pp. 991-1005, September 1993, doi: .
Abstract: System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_9_991/_p

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@ARTICLE{e76-d_9_991,
author={Fadi J. KURDAHI, Daniel D. GAJSKI, Champaka RAMACHANDRAN, Viraphol CHAIYAKUL, },
journal={IEICE TRANSACTIONS on Information},
title={Linking Register-Transfer and Physical Levels of Design},
year={1993},
volume={E76-D},
number={9},
pages={991-1005},
abstract={System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Linking Register-Transfer and Physical Levels of Design
T2 - IEICE TRANSACTIONS on Information
SP - 991
EP - 1005
AU - Fadi J. KURDAHI
AU - Daniel D. GAJSKI
AU - Champaka RAMACHANDRAN
AU - Viraphol CHAIYAKUL
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1993
AB - System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.
ER -