IEICE TRANSACTIONS on Information
High-Level Synthesis for Weakly Testable Data Paths
Summary :
We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.
- Publication
- IEICE TRANSACTIONS on Information Vol.E81-D No.7 pp.645-653
- Publication Date
- 1998/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
- Category
- Test Synthesis
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Keyword
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Michiko INOUE, Kenji NODA, Takeshi HIGASHIMURA, Toshimitsu MASUZAWA, Hideo FUJIWARA, "High-Level Synthesis for Weakly Testable Data Paths" in IEICE TRANSACTIONS on Information,
vol. E81-D, no. 7, pp. 645-653, July 1998, doi: .
Abstract: We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.
URL: https://global.ieice.org/en_transactions/information/10.1587/e81-d_7_645/_p
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@ARTICLE{e81-d_7_645,
author={Michiko INOUE, Kenji NODA, Takeshi HIGASHIMURA, Toshimitsu MASUZAWA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={High-Level Synthesis for Weakly Testable Data Paths},
year={1998},
volume={E81-D},
number={7},
pages={645-653},
abstract={We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - High-Level Synthesis for Weakly Testable Data Paths
T2 - IEICE TRANSACTIONS on Information
SP - 645
EP - 653
AU - Michiko INOUE
AU - Kenji NODA
AU - Takeshi HIGASHIMURA
AU - Toshimitsu MASUZAWA
AU - Hideo FUJIWARA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E81-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1998
AB - We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.
ER -
English
