EB-Testing-Pad Method and its Evaluation by Actual Devices

Norio KUJI; Takako ISHIHARA; Shigeru NAKAJIMA

EB-Testing-Pad Method and its Evaluation by Actual Devices

Norio KUJI, Takako ISHIHARA, Shigeru NAKAJIMA

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A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.

Publication: IEICE TRANSACTIONS on Information Vol.E85-D No.10 pp.1558-1563

Publication Date: 2002/10/01

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Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)

Category: EB Tester

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Norio KUJI, Takako ISHIHARA, Shigeru NAKAJIMA, "EB-Testing-Pad Method and its Evaluation by Actual Devices" in IEICE TRANSACTIONS on Information, vol. E85-D, no. 10, pp. 1558-1563, October 2002, doi: .
Abstract: A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1558/_p

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@ARTICLE{e85-d_10_1558,
author={Norio KUJI, Takako ISHIHARA, Shigeru NAKAJIMA, },
journal={IEICE TRANSACTIONS on Information},
title={EB-Testing-Pad Method and its Evaluation by Actual Devices},
year={2002},
volume={E85-D},
number={10},
pages={1558-1563},
abstract={A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - EB-Testing-Pad Method and its Evaluation by Actual Devices
T2 - IEICE TRANSACTIONS on Information
SP - 1558
EP - 1563
AU - Norio KUJI
AU - Takako ISHIHARA
AU - Shigeru NAKAJIMA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.
ER -