A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation

Makoto SYUTO; Eriko SATAKE; Koichi TANNO; Okihiko ISHIZUKA

A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation

Makoto SYUTO, Eriko SATAKE, Koichi TANNO, Okihiko ISHIZUKA

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In this letter, we propose high-speed binary to residue converters for moduli 2ⁿ, 2ⁿ 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 2¹⁰-1 and 1.73 ns for modulus 2¹⁰+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 2¹⁰ 1 is 335 µm325 µm.

Publication: IEICE TRANSACTIONS on Information Vol.E85-D No.5 pp.903-905

Publication Date: 2002/05/01

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Type of Manuscript: LETTER

Category: VLSI Systems

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Makoto SYUTO, Eriko SATAKE, Koichi TANNO, Okihiko ISHIZUKA, "A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation" in IEICE TRANSACTIONS on Information, vol. E85-D, no. 5, pp. 903-905, May 2002, doi: .
Abstract: In this letter, we propose high-speed binary to residue converters for moduli 2ⁿ, 2ⁿ 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 2¹⁰-1 and 1.73 ns for modulus 2¹⁰+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 2¹⁰ 1 is 335 µm325 µm.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_5_903/_p

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@ARTICLE{e85-d_5_903,
author={Makoto SYUTO, Eriko SATAKE, Koichi TANNO, Okihiko ISHIZUKA, },
journal={IEICE TRANSACTIONS on Information},
title={A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation},
year={2002},
volume={E85-D},
number={5},
pages={903-905},
abstract={In this letter, we propose high-speed binary to residue converters for moduli 2ⁿ, 2ⁿ 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 2¹⁰-1 and 1.73 ns for modulus 2¹⁰+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 2¹⁰ 1 is 335 µm325 µm.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation
T2 - IEICE TRANSACTIONS on Information
SP - 903
EP - 905
AU - Makoto SYUTO
AU - Eriko SATAKE
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2002
AB - In this letter, we propose high-speed binary to residue converters for moduli 2ⁿ, 2ⁿ 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 2¹⁰-1 and 1.73 ns for modulus 2¹⁰+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 2¹⁰ 1 is 335 µm325 µm.
ER -