A High-Speed Binary to Residue Converter Using a Signed-Digit Number Representation

Makoto SYUTO, Eriko SATAKE, Koichi TANNO, Okihiko ISHIZUKA

Summary :

In this letter, we propose high-speed binary to residue converters for moduli 2ⁿ, 2ⁿ 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 2¹⁰-1 and 1.73 ns for modulus 2¹⁰+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 2¹⁰ 1 is 335 µm325 µm.

• Publication: IEICE TRANSACTIONS on Information Vol.E85-D No.5 pp.903-905
• Publication Date: 2002/05/01
• Type of Manuscript: LETTER
• Category: VLSI Systems

Authors

Makoto SYUTO
Eriko SATAKE
Koichi TANNO
Okihiko ISHIZUKA

Keyword

residue number system,  signed-digit number representation,  binary to residue converter,  carry-free addition