Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis

Dong XIANG; Shan GU; Hideo FUJIWARA

Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis

Dong XIANG, Shan GU, Hideo FUJIWARA

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A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.

Publication: IEICE TRANSACTIONS on Information Vol.E86-D No.11 pp.2407-2417

Publication Date: 2003/11/01

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Type of Manuscript: PAPER

Category: Fault Tolerance

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Dong XIANG, Shan GU, Hideo FUJIWARA, "Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis" in IEICE TRANSACTIONS on Information, vol. E86-D, no. 11, pp. 2407-2417, November 2003, doi: .
Abstract: A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_11_2407/_p

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@ARTICLE{e86-d_11_2407,
author={Dong XIANG, Shan GU, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis},
year={2003},
volume={E86-D},
number={11},
pages={2407-2417},
abstract={A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
T2 - IEICE TRANSACTIONS on Information
SP - 2407
EP - 2417
AU - Dong XIANG
AU - Shan GU
AU - Hideo FUJIWARA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2003
AB - A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.
ER -