Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity

Takashi KAWANAMI; Masakazu HIOKI; Hiroshi NAGASE; Toshiyuki TSUTSUMI; Tadashi NAKAGAWA; Toshihiro SEKIGAWA; Hanpei KOIKE

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity

Takashi KAWANAMI, Masakazu HIOKI, Hiroshi NAGASE, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA, Hanpei KOIKE

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The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.

Publication: IEICE TRANSACTIONS on Information Vol.E87-D No.8 pp.2004-2010

Publication Date: 2004/08/01

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Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)

Category: Recornfigurable Systems

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Takashi KAWANAMI, Masakazu HIOKI, Hiroshi NAGASE, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA, Hanpei KOIKE, "Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity" in IEICE TRANSACTIONS on Information, vol. E87-D, no. 8, pp. 2004-2010, August 2004, doi: .
Abstract: The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_8_2004/_p

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@ARTICLE{e87-d_8_2004,
author={Takashi KAWANAMI, Masakazu HIOKI, Hiroshi NAGASE, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA, Hanpei KOIKE, },
journal={IEICE TRANSACTIONS on Information},
title={Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity},
year={2004},
volume={E87-D},
number={8},
pages={2004-2010},
abstract={The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity
T2 - IEICE TRANSACTIONS on Information
SP - 2004
EP - 2010
AU - Takashi KAWANAMI
AU - Masakazu HIOKI
AU - Hiroshi NAGASE
AU - Toshiyuki TSUTSUMI
AU - Tadashi NAKAGAWA
AU - Toshihiro SEKIGAWA
AU - Hanpei KOIKE
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2004
AB - The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.
ER -