IEICE TRANSACTIONS on Information
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
Summary :
With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.
- Publication
- IEICE TRANSACTIONS on Information Vol.E97-D No.10 pp.2719-2729
- Publication Date
- 2014/10/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014EDP7110
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Wenpo ZHANG
Chiba University
Kazuteru NAMBA
Chiba University
Hideo ITO
Chiba University
Keyword
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Wenpo ZHANG, Kazuteru NAMBA, Hideo ITO, "Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 10, pp. 2719-2729, October 2014, doi: 10.1587/transinf.2014EDP7110.
Abstract: With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014EDP7110/_p
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@ARTICLE{e97-d_10_2719,
author={Wenpo ZHANG, Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion},
year={2014},
volume={E97-D},
number={10},
pages={2719-2729},
abstract={With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.},
keywords={},
doi={10.1587/transinf.2014EDP7110},
ISSN={1745-1361},
month={October},}
Copy
TY - JOUR
TI - Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
T2 - IEICE TRANSACTIONS on Information
SP - 2719
EP - 2729
AU - Wenpo ZHANG
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2014
DO - 10.1587/transinf.2014EDP7110
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2014
AB - With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.
ER -
English
