Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Motoki AMAGASAKI; Yuki NISHITANI; Kazuki INOUE; Masahiro IIDA; Morihiro KUGA; Toshinori SUEYOSHI

doi:10.1587/transinf.2016AWI0005

IEICE TRANSACTIONS on Information

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Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Motoki AMAGASAKI, Yuki NISHITANI, Kazuki INOUE, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI

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Summary :

Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.

Publication: IEICE TRANSACTIONS on Information Vol.E100-D No.4 pp.633-644

Publication Date: 2017/04/01

Publicized: 2017/01/13

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2016AWI0005

Type of Manuscript: Special Section INVITED PAPER (Special Section on Award-winning Papers)

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Authors

Motoki AMAGASAKI
  Kumamoto University
Yuki NISHITANI
  Kumamoto University
Kazuki INOUE
  Kumamoto University
Masahiro IIDA
  Kumamoto University
Morihiro KUGA
  Kumamoto University
Toshinori SUEYOSHI
  Kumamoto University

Keyword

fault tolerant, fault recovery, FPGA-IP

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Motoki AMAGASAKI, Yuki NISHITANI, Kazuki INOUE, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, "Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core" in IEICE TRANSACTIONS on Information, vol. E100-D, no. 4, pp. 633-644, April 2017, doi: 10.1587/transinf.2016AWI0005.
Abstract: Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2016AWI0005/_p

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@ARTICLE{e100-d_4_633,
author={Motoki AMAGASAKI, Yuki NISHITANI, Kazuki INOUE, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core},
year={2017},
volume={E100-D},
number={4},
pages={633-644},
abstract={Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.},
keywords={},
doi={10.1587/transinf.2016AWI0005},
ISSN={1745-1361},
month={April},}

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TY - JOUR
TI - Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core
T2 - IEICE TRANSACTIONS on Information
SP - 633
EP - 644
AU - Motoki AMAGASAKI
AU - Yuki NISHITANI
AU - Kazuki INOUE
AU - Masahiro IIDA
AU - Morihiro KUGA
AU - Toshinori SUEYOSHI
PY - 2017
DO - 10.1587/transinf.2016AWI0005
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2017
AB - Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.
ER -

IEICE TRANSACTIONS on Information