IEICE TRANSACTIONS on Information
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs
Summary :
The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.
- Publication
- IEICE TRANSACTIONS on Information Vol.E101-D No.9 pp.2247-2257
- Publication Date
- 2018/09/01
- Publicized
- 2018/06/08
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2017EDP7296
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Satoshi IMAMURA
Fujitsu Laboratories Ltd.
Yuichiro YASUI
Kyushu University
Koji INOUE
Kyushu University
Takatsugu ONO
Kyushu University
Hiroshi SASAKI
Columbia University
Katsuki FUJISAWA
Kyushu University
Keyword
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Satoshi IMAMURA, Yuichiro YASUI, Koji INOUE, Takatsugu ONO, Hiroshi SASAKI, Katsuki FUJISAWA, "Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 9, pp. 2247-2257, September 2018, doi: 10.1587/transinf.2017EDP7296.
Abstract: The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017EDP7296/_p
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@ARTICLE{e101-d_9_2247,
author={Satoshi IMAMURA, Yuichiro YASUI, Koji INOUE, Takatsugu ONO, Hiroshi SASAKI, Katsuki FUJISAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs},
year={2018},
volume={E101-D},
number={9},
pages={2247-2257},
abstract={The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.},
keywords={},
doi={10.1587/transinf.2017EDP7296},
ISSN={1745-1361},
month={September},}
Copy
TY - JOUR
TI - Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs
T2 - IEICE TRANSACTIONS on Information
SP - 2247
EP - 2257
AU - Satoshi IMAMURA
AU - Yuichiro YASUI
AU - Koji INOUE
AU - Takatsugu ONO
AU - Hiroshi SASAKI
AU - Katsuki FUJISAWA
PY - 2018
DO - 10.1587/transinf.2017EDP7296
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2018
AB - The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality(RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5% on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.
ER -
English
