IEICE TRANSACTIONS on Information
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
Summary :
A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.
- Publication
- IEICE TRANSACTIONS on Information Vol.E101-D No.8 pp.2053-2063
- Publication Date
- 2018/08/01
- Publicized
- 2018/05/09
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2018EDP7093
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Fara ASHIKIN
Tokushima University,Universiti Teknikal Malaysia Melaka
Masaki HASHIZUME
Tokushima University
Hiroyuki YOTSUYANAGI
Tokushima University
Shyue-Kung LU
National Taiwan University of Science and Technology
Zvi ROTH
Florida Atlantic University
Keyword
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Fara ASHIKIN, Masaki HASHIZUME, Hiroyuki YOTSUYANAGI, Shyue-Kung LU, Zvi ROTH, "A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 8, pp. 2053-2063, August 2018, doi: 10.1587/transinf.2018EDP7093.
Abstract: A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7093/_p
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@ARTICLE{e101-d_8_2053,
author={Fara ASHIKIN, Masaki HASHIZUME, Hiroyuki YOTSUYANAGI, Shyue-Kung LU, Zvi ROTH, },
journal={IEICE TRANSACTIONS on Information},
title={A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs},
year={2018},
volume={E101-D},
number={8},
pages={2053-2063},
abstract={A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.},
keywords={},
doi={10.1587/transinf.2018EDP7093},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
T2 - IEICE TRANSACTIONS on Information
SP - 2053
EP - 2063
AU - Fara ASHIKIN
AU - Masaki HASHIZUME
AU - Hiroyuki YOTSUYANAGI
AU - Shyue-Kung LU
AU - Zvi ROTH
PY - 2018
DO - 10.1587/transinf.2018EDP7093
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2018
AB - A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.
ER -
English
