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New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
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- IEICE TRANSACTIONS on Information Vol.0 No.0 pp.0-0
- Publicized
- 2024/05/10
- DOI
- 10.1587/10.1587/transinf.2023LOP0003
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Takashi HIRAYAMA, Rin SUZUKI, Katsuhisa YAMANAKA, Yasuaki NISHITANI, "New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits" in IEICE TRANSACTIONS on Information,
vol. , no. 0, pp. 0-0, January , doi: 10.1587/10.1587/transinf.2023LOP0003.
Abstract:
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023LOP0003/_advpub_f
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@ARTICLE{2023LOP0003,
author={Takashi HIRAYAMA, Rin SUZUKI, Katsuhisa YAMANAKA, Yasuaki NISHITANI, },
journal={IEICE TRANSACTIONS on Information},
title={New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits},
year={},
volume={},
number={0},
pages={0-0},
abstract={},
keywords={},
doi={10.1587/10.1587/transinf.2023LOP0003},
ISSN={},
month={January},}
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TY - JOUR
TI - New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 0
EP - 0
AU - Takashi HIRAYAMA
AU - Rin SUZUKI
AU - Katsuhisa YAMANAKA
AU - Yasuaki NISHITANI
PY -
DO - 10.1587/10.1587/transinf.2023LOP0003
JO - IEICE TRANSACTIONS on Information
SN -
VL -
IS - 0
JA - IEICE TRANSACTIONS on Information
Y1 - January
AB -
ER -
English
