Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
Summary :
It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.
- Publication
- IEICE TRANSACTIONS on Information Vol.E94-D No.7 pp.1430-1439
- Publication Date
- 2011/07/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E94.D.1430
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Katsuya FUJIWARA, Hideo FUJIWARA, Hideo TAMAMOTO, "Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 7, pp. 1430-1439, July 2011, doi: 10.1587/transinf.E94.D.1430.
Abstract: It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1430/_p
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@ARTICLE{e94-d_7_1430,
author={Katsuya FUJIWARA, Hideo FUJIWARA, Hideo TAMAMOTO, },
journal={IEICE TRANSACTIONS on Information},
title={Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design},
year={2011},
volume={E94-D},
number={7},
pages={1430-1439},
abstract={It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.},
keywords={},
doi={10.1587/transinf.E94.D.1430},
ISSN={1745-1361},
month={July},}
Copy
TY - JOUR
TI - Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
T2 - IEICE TRANSACTIONS on Information
SP - 1430
EP - 1439
AU - Katsuya FUJIWARA
AU - Hideo FUJIWARA
AU - Hideo TAMAMOTO
PY - 2011
DO - 10.1587/transinf.E94.D.1430
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2011
AB - It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.
ER -
English
