Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

Ming-Der SHIEH; Shih-Hao FANG; Shing-Chung TANG; Der-Wei YANG

doi:10.1587/transinf.E95.D.549

Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

Ming-Der SHIEH, Shih-Hao FANG, Shing-Chung TANG, Der-Wei YANG

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Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.549-557

Publication Date: 2012/02/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.549

Type of Manuscript: PAPER

Category: Computer System

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Ming-Der SHIEH, Shih-Hao FANG, Shing-Chung TANG, Der-Wei YANG, "Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 2, pp. 549-557, February 2012, doi: 10.1587/transinf.E95.D.549.
Abstract: Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.549/_p

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@ARTICLE{e95-d_2_549,
author={Ming-Der SHIEH, Shih-Hao FANG, Shing-Chung TANG, Der-Wei YANG, },
journal={IEICE TRANSACTIONS on Information},
title={Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders},
year={2012},
volume={E95-D},
number={2},
pages={549-557},
abstract={Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.},
keywords={},
doi={10.1587/transinf.E95.D.549},
ISSN={1745-1361},
month={February},}

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TY - JOUR
TI - Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders
T2 - IEICE TRANSACTIONS on Information
SP - 549
EP - 557
AU - Ming-Der SHIEH
AU - Shih-Hao FANG
AU - Shing-Chung TANG
AU - Der-Wei YANG
PY - 2012
DO - 10.1587/transinf.E95.D.549
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.
ER -