Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

A blind channel estimation algorithm based on the subspace method for single-input multiple-output (SIMO) orthogonal frequency division multiplexing (OFDM) systems is proposed in this letter. With the aid of a repetition index, the conventional algorithm is a special case of our algorithm. Compared with related studies, the proposed algorithm reduces the computational complexity of the SVD operation and is suitable for cyclic-prefix-free systems. In particular, the necessary condition of the proposed signal matrix to be full rank can be satisfied with fewer OFDM blocks. Simulation results demonstrate that the proposed algorithm outperforms conventional methods in normalized mean-square error.