IEICE TRANSACTIONS on Information
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
Summary :
As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.25
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.5 pp.1219-1222
- Publication Date
- 2013/05/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.1219
- Type of Manuscript
- LETTER
- Category
- Dependable Computing
Authors
Keyword
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Wenpo ZHANG, Kazuteru NAMBA, Hideo ITO, "Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 5, pp. 1219-1222, May 2013, doi: 10.1587/transinf.E96.D.1219.
Abstract: As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.25
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1219/_p
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@ARTICLE{e96-d_5_1219,
author={Wenpo ZHANG, Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF},
year={2013},
volume={E96-D},
number={5},
pages={1219-1222},
abstract={As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.25
keywords={},
doi={10.1587/transinf.E96.D.1219},
ISSN={1745-1361},
month={May},}
Copy
TY - JOUR
TI - Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
T2 - IEICE TRANSACTIONS on Information
SP - 1219
EP - 1222
AU - Wenpo ZHANG
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2013
DO - 10.1587/transinf.E96.D.1219
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2013
AB - As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.25
ER -
English
