Filter caches have been studied as an energy efficient solution. They achieve energy savings via selected access to L1 cache, but severely decrease system performance. Therefore, a filter cache system should adopt components that balance execution delay against energy savings. In this letter, we analyze the legacy filter cache system and propose Data Filter Cache with Partial Tag Cache (DFPC) as a new solution. The proposed DFPC scheme reduces energy consumption of L1 data cache and does not impair system performance at all. Simulation results show that DFPC provides the 46.36% energy savings without any performance loss.
Ju Hee CHOI
Seoul National University
Jong Wook KWAK
Yeungnam University
Seong Tae JHANG
The University of Suwon
Chu Shik JHON
Seoul National University
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Ju Hee CHOI, Jong Wook KWAK, Seong Tae JHANG, Chu Shik JHON, "Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 4, pp. 972-975, April 2014, doi: 10.1587/transinf.E97.D.972.
Abstract: Filter caches have been studied as an energy efficient solution. They achieve energy savings via selected access to L1 cache, but severely decrease system performance. Therefore, a filter cache system should adopt components that balance execution delay against energy savings. In this letter, we analyze the legacy filter cache system and propose Data Filter Cache with Partial Tag Cache (DFPC) as a new solution. The proposed DFPC scheme reduces energy consumption of L1 data cache and does not impair system performance at all. Simulation results show that DFPC provides the 46.36% energy savings without any performance loss.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E97.D.972/_p
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@ARTICLE{e97-d_4_972,
author={Ju Hee CHOI, Jong Wook KWAK, Seong Tae JHANG, Chu Shik JHON, },
journal={IEICE TRANSACTIONS on Information},
title={Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor},
year={2014},
volume={E97-D},
number={4},
pages={972-975},
abstract={Filter caches have been studied as an energy efficient solution. They achieve energy savings via selected access to L1 cache, but severely decrease system performance. Therefore, a filter cache system should adopt components that balance execution delay against energy savings. In this letter, we analyze the legacy filter cache system and propose Data Filter Cache with Partial Tag Cache (DFPC) as a new solution. The proposed DFPC scheme reduces energy consumption of L1 data cache and does not impair system performance at all. Simulation results show that DFPC provides the 46.36% energy savings without any performance loss.},
keywords={},
doi={10.1587/transinf.E97.D.972},
ISSN={1745-1361},
month={April},}
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TY - JOUR
TI - Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor
T2 - IEICE TRANSACTIONS on Information
SP - 972
EP - 975
AU - Ju Hee CHOI
AU - Jong Wook KWAK
AU - Seong Tae JHANG
AU - Chu Shik JHON
PY - 2014
DO - 10.1587/transinf.E97.D.972
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2014
AB - Filter caches have been studied as an energy efficient solution. They achieve energy savings via selected access to L1 cache, but severely decrease system performance. Therefore, a filter cache system should adopt components that balance execution delay against energy savings. In this letter, we analyze the legacy filter cache system and propose Data Filter Cache with Partial Tag Cache (DFPC) as a new solution. The proposed DFPC scheme reduces energy consumption of L1 data cache and does not impair system performance at all. Simulation results show that DFPC provides the 46.36% energy savings without any performance loss.
ER -