Error Control for Byte-per-Package Organized Memory Systems

Eiji FUJIWARA

Error Control for Byte-per-Package Organized Memory Systems

Eiji FUJIWARA

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Error correcting and/or error detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bit per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bit as a byte. This paper provides a new class of binary error correcting codes to correct single bit errors and detect single byte errors (SEC-S_b ED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-S_b ED codes). Also, an improved byte error correction method which is called erasure correction method is proposed using the SEC-S_b ED codes. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting-Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes. The proposed SEC-DED-S_b ED codes for b4 require about one more check bit and for b8 require about four more check bits than SEC-DED codes.

Publication: IEICE TRANSACTIONS on transactions Vol.E63-E No.2 pp.98-103

Publication Date: 1980/02/25

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Type of Manuscript: PAPER

Category: Computers

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Eiji FUJIWARA

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Eiji FUJIWARA, "Error Control for Byte-per-Package Organized Memory Systems" in IEICE TRANSACTIONS on transactions, vol. E63-E, no. 2, pp. 98-103, February 1980, doi: .
Abstract: Error correcting and/or error detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bit per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bit as a byte. This paper provides a new class of binary error correcting codes to correct single bit errors and detect single byte errors (SEC-S_b ED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-S_b ED codes). Also, an improved byte error correction method which is called erasure correction method is proposed using the SEC-S_b ED codes. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting-Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes. The proposed SEC-DED-S_b ED codes for b4 require about one more check bit and for b8 require about four more check bits than SEC-DED codes.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e63-e_2_98/_p

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@ARTICLE{e63-e_2_98,
author={Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on transactions},
title={Error Control for Byte-per-Package Organized Memory Systems},
year={1980},
volume={E63-E},
number={2},
pages={98-103},
abstract={Error correcting and/or error detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bit per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bit as a byte. This paper provides a new class of binary error correcting codes to correct single bit errors and detect single byte errors (SEC-S_b ED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-S_b ED codes). Also, an improved byte error correction method which is called erasure correction method is proposed using the SEC-S_b ED codes. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting-Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes. The proposed SEC-DED-S_b ED codes for b4 require about one more check bit and for b8 require about four more check bits than SEC-DED codes.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Error Control for Byte-per-Package Organized Memory Systems
T2 - IEICE TRANSACTIONS on transactions
SP - 98
EP - 103
AU - Eiji FUJIWARA
PY - 1980
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E63-E
IS - 2
JA - IEICE TRANSACTIONS on transactions
Y1 - February 1980
AB - Error correcting and/or error detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bit per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bit as a byte. This paper provides a new class of binary error correcting codes to correct single bit errors and detect single byte errors (SEC-S_b ED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-S_b ED codes). Also, an improved byte error correction method which is called erasure correction method is proposed using the SEC-S_b ED codes. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting-Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes. The proposed SEC-DED-S_b ED codes for b4 require about one more check bit and for b8 require about four more check bits than SEC-DED codes.
ER -