A New Addressing Scheme with Reorganizable Memory Structure--Basic Principle--
Summary :
In a multiprocessor system where the number of processors composing the system is increased, and the memory utilization is raised by improving the execution rate of each processor, the reduction of system throughput caused by the memory access conflicts has to be considered substantially. This paper describes the discussion on such an approach that implements a conflict-free data mapping by the use of some sophisticated address translation between logical and physical addresses. This new addressing scheme of a reorganizable memory structure provides the function that allows each processor easily to distribute the operands to be accessed to completely different memory modules, by interlaying the address translation mechanism called address organizer between logical and physical addresses. This approach permits the memory structure to reorganize so as to make it adaptive to the parallelism contained in the problems themselves, and thus also to accomplish the suppression of memory access conflicts spontaneously. Furthermore, conflict-free data mapping being eventually accomplished through an interface of such a hardware as address translation mechanism, this approach has an advantage that the user's logical address space will not be affected in the least.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E65-E No.8 pp.464-471
- Publication Date
- 1982/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Computers
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Shigenori SHIMIZU, Misao KITAGAWA, "A New Addressing Scheme with Reorganizable Memory Structure--Basic Principle--" in IEICE TRANSACTIONS on transactions,
vol. E65-E, no. 8, pp. 464-471, August 1982, doi: .
Abstract: In a multiprocessor system where the number of processors composing the system is increased, and the memory utilization is raised by improving the execution rate of each processor, the reduction of system throughput caused by the memory access conflicts has to be considered substantially. This paper describes the discussion on such an approach that implements a conflict-free data mapping by the use of some sophisticated address translation between logical and physical addresses. This new addressing scheme of a reorganizable memory structure provides the function that allows each processor easily to distribute the operands to be accessed to completely different memory modules, by interlaying the address translation mechanism called address organizer between logical and physical addresses. This approach permits the memory structure to reorganize so as to make it adaptive to the parallelism contained in the problems themselves, and thus also to accomplish the suppression of memory access conflicts spontaneously. Furthermore, conflict-free data mapping being eventually accomplished through an interface of such a hardware as address translation mechanism, this approach has an advantage that the user's logical address space will not be affected in the least.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e65-e_8_464/_p
Copy
@ARTICLE{e65-e_8_464,
author={Shigenori SHIMIZU, Misao KITAGAWA, },
journal={IEICE TRANSACTIONS on transactions},
title={A New Addressing Scheme with Reorganizable Memory Structure--Basic Principle--},
year={1982},
volume={E65-E},
number={8},
pages={464-471},
abstract={In a multiprocessor system where the number of processors composing the system is increased, and the memory utilization is raised by improving the execution rate of each processor, the reduction of system throughput caused by the memory access conflicts has to be considered substantially. This paper describes the discussion on such an approach that implements a conflict-free data mapping by the use of some sophisticated address translation between logical and physical addresses. This new addressing scheme of a reorganizable memory structure provides the function that allows each processor easily to distribute the operands to be accessed to completely different memory modules, by interlaying the address translation mechanism called address organizer between logical and physical addresses. This approach permits the memory structure to reorganize so as to make it adaptive to the parallelism contained in the problems themselves, and thus also to accomplish the suppression of memory access conflicts spontaneously. Furthermore, conflict-free data mapping being eventually accomplished through an interface of such a hardware as address translation mechanism, this approach has an advantage that the user's logical address space will not be affected in the least.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A New Addressing Scheme with Reorganizable Memory Structure--Basic Principle--
T2 - IEICE TRANSACTIONS on transactions
SP - 464
EP - 471
AU - Shigenori SHIMIZU
AU - Misao KITAGAWA
PY - 1982
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E65-E
IS - 8
JA - IEICE TRANSACTIONS on transactions
Y1 - August 1982
AB - In a multiprocessor system where the number of processors composing the system is increased, and the memory utilization is raised by improving the execution rate of each processor, the reduction of system throughput caused by the memory access conflicts has to be considered substantially. This paper describes the discussion on such an approach that implements a conflict-free data mapping by the use of some sophisticated address translation between logical and physical addresses. This new addressing scheme of a reorganizable memory structure provides the function that allows each processor easily to distribute the operands to be accessed to completely different memory modules, by interlaying the address translation mechanism called address organizer between logical and physical addresses. This approach permits the memory structure to reorganize so as to make it adaptive to the parallelism contained in the problems themselves, and thus also to accomplish the suppression of memory access conflicts spontaneously. Furthermore, conflict-free data mapping being eventually accomplished through an interface of such a hardware as address translation mechanism, this approach has an advantage that the user's logical address space will not be affected in the least.
ER -
English
