IEICE TRANSACTIONS on transactions
A New Addressing Scheme with Reorganizable Memory Structure--Application Algorithms--
Summary :
It is well known in a multiprocessor system that the reduction of the system throughput is chiefly attributable to its memory access conflicts. A new method has been proposed which can avoid the memory access conflicts by means of realizing a conflict-free data mapping through a new technique of reorganizable memory structure. On the other hand, whether or not a parallel processing system is successful does deeply depend on the software design. Most of the algorithms for numeric computations are not suitable for the parallel processing, but usually for the sequential one; accordingly, it is important to develop such an algorithm that takes account of its parallelism. This paper describes some examples of parallel processing algorithms suitable for the proposed multiprocessor system with reorganizable memory structure. The application problems described in this paper involve the fast Fourier transform and the matricx processing, but these are only an example or two out of many application problems. By the use of algorithms as mentioned in this paper, the multiprocessor system with reorganizable memory system can demonstrate its effectiveness and perform the parallel processing without any memory access conflicts.
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- IEICE TRANSACTIONS on transactions Vol.E65-E No.8 pp.472-479
- Publication Date
- 1982/08/25
- Publicized
- Online ISSN
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- Type of Manuscript
- PAPER
- Category
- Computers
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Shigenori SHIMIZU, Misao KITAGAWA, "A New Addressing Scheme with Reorganizable Memory Structure--Application Algorithms--" in IEICE TRANSACTIONS on transactions,
vol. E65-E, no. 8, pp. 472-479, August 1982, doi: .
Abstract: It is well known in a multiprocessor system that the reduction of the system throughput is chiefly attributable to its memory access conflicts. A new method has been proposed which can avoid the memory access conflicts by means of realizing a conflict-free data mapping through a new technique of reorganizable memory structure. On the other hand, whether or not a parallel processing system is successful does deeply depend on the software design. Most of the algorithms for numeric computations are not suitable for the parallel processing, but usually for the sequential one; accordingly, it is important to develop such an algorithm that takes account of its parallelism. This paper describes some examples of parallel processing algorithms suitable for the proposed multiprocessor system with reorganizable memory structure. The application problems described in this paper involve the fast Fourier transform and the matricx processing, but these are only an example or two out of many application problems. By the use of algorithms as mentioned in this paper, the multiprocessor system with reorganizable memory system can demonstrate its effectiveness and perform the parallel processing without any memory access conflicts.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e65-e_8_472/_p
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@ARTICLE{e65-e_8_472,
author={Shigenori SHIMIZU, Misao KITAGAWA, },
journal={IEICE TRANSACTIONS on transactions},
title={A New Addressing Scheme with Reorganizable Memory Structure--Application Algorithms--},
year={1982},
volume={E65-E},
number={8},
pages={472-479},
abstract={It is well known in a multiprocessor system that the reduction of the system throughput is chiefly attributable to its memory access conflicts. A new method has been proposed which can avoid the memory access conflicts by means of realizing a conflict-free data mapping through a new technique of reorganizable memory structure. On the other hand, whether or not a parallel processing system is successful does deeply depend on the software design. Most of the algorithms for numeric computations are not suitable for the parallel processing, but usually for the sequential one; accordingly, it is important to develop such an algorithm that takes account of its parallelism. This paper describes some examples of parallel processing algorithms suitable for the proposed multiprocessor system with reorganizable memory structure. The application problems described in this paper involve the fast Fourier transform and the matricx processing, but these are only an example or two out of many application problems. By the use of algorithms as mentioned in this paper, the multiprocessor system with reorganizable memory system can demonstrate its effectiveness and perform the parallel processing without any memory access conflicts.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A New Addressing Scheme with Reorganizable Memory Structure--Application Algorithms--
T2 - IEICE TRANSACTIONS on transactions
SP - 472
EP - 479
AU - Shigenori SHIMIZU
AU - Misao KITAGAWA
PY - 1982
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E65-E
IS - 8
JA - IEICE TRANSACTIONS on transactions
Y1 - August 1982
AB - It is well known in a multiprocessor system that the reduction of the system throughput is chiefly attributable to its memory access conflicts. A new method has been proposed which can avoid the memory access conflicts by means of realizing a conflict-free data mapping through a new technique of reorganizable memory structure. On the other hand, whether or not a parallel processing system is successful does deeply depend on the software design. Most of the algorithms for numeric computations are not suitable for the parallel processing, but usually for the sequential one; accordingly, it is important to develop such an algorithm that takes account of its parallelism. This paper describes some examples of parallel processing algorithms suitable for the proposed multiprocessor system with reorganizable memory structure. The application problems described in this paper involve the fast Fourier transform and the matricx processing, but these are only an example or two out of many application problems. By the use of algorithms as mentioned in this paper, the multiprocessor system with reorganizable memory system can demonstrate its effectiveness and perform the parallel processing without any memory access conflicts.
ER -
English
