Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions
Summary :
In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero imput limit cycles.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E70-E No.4 pp.373-375
- Publication Date
- 1987/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Circuit Theory
Authors
Keyword
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Masayuki KAWAMATA, Tatsuo HIGUCHI, "Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions" in IEICE TRANSACTIONS on transactions,
vol. E70-E, no. 4, pp. 373-375, April 1987, doi: .
Abstract: In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero imput limit cycles.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e70-e_4_373/_p
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@ARTICLE{e70-e_4_373,
author={Masayuki KAWAMATA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on transactions},
title={Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions},
year={1987},
volume={E70-E},
number={4},
pages={373-375},
abstract={In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero imput limit cycles.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions
T2 - IEICE TRANSACTIONS on transactions
SP - 373
EP - 375
AU - Masayuki KAWAMATA
AU - Tatsuo HIGUCHI
PY - 1987
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E70-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1987
AB - In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero imput limit cycles.
ER -
English
