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Yasuaki NISHITANI, Kensuke SHIMIZU, "Multilevel Network Design for Parity Functions with MOS Cells under Limitations on the Number of Series Transistors" in IEICE TRANSACTIONS on transactions,
vol. E71-E, no. 8, pp. 791-798, August 1988, doi: .
Abstract: A design method of multilevel logic networks, in single-rail input logic, with MOS cells for parity functions of n variables is presented. The parity functions x1x2xn in a two level network requires 2n-1+1 gates, whereas the number of NOR gates in a multilevel network for this function is proportional to n. Since MOS cells are playing a major role in LSI and can represent more complex functions than a NOR or a NAND gate, it is possible to obtain smaller networks with complex MOS cells than with NOR or NAND gates. However, if MOS cells become excessively complex, the propagation delay time of MOS cells is too large and the normal operation of the whole MOS network cannot be expected. The design procedure given in this paper is systematic and very easy to apply. In the beginning, the formulation of MOS cells and MOS networks has been presented. In this formulation, the number of series and parallel transistors and the number of MOS cells and levels can be defined and enumerated for MOS networks. Without the restrictions the maximum number of series transistors is the number of input variables, n. With the estriction on the number of series transistors to R, the number of parallel transistors is less than or equal to 2R-1. Furthermore, the number of MOS cells and the number of levels of the MOS network are proportional to n and logRn, respectively. Since the designed network is similar to a complete tree, it would also be useful to process a series of combinations of input variable values.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e71-e_8_791/_p
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@ARTICLE{e71-e_8_791,
author={Yasuaki NISHITANI, Kensuke SHIMIZU, },
journal={IEICE TRANSACTIONS on transactions},
title={Multilevel Network Design for Parity Functions with MOS Cells under Limitations on the Number of Series Transistors},
year={1988},
volume={E71-E},
number={8},
pages={791-798},
abstract={A design method of multilevel logic networks, in single-rail input logic, with MOS cells for parity functions of n variables is presented. The parity functions x1x2xn in a two level network requires 2n-1+1 gates, whereas the number of NOR gates in a multilevel network for this function is proportional to n. Since MOS cells are playing a major role in LSI and can represent more complex functions than a NOR or a NAND gate, it is possible to obtain smaller networks with complex MOS cells than with NOR or NAND gates. However, if MOS cells become excessively complex, the propagation delay time of MOS cells is too large and the normal operation of the whole MOS network cannot be expected. The design procedure given in this paper is systematic and very easy to apply. In the beginning, the formulation of MOS cells and MOS networks has been presented. In this formulation, the number of series and parallel transistors and the number of MOS cells and levels can be defined and enumerated for MOS networks. Without the restrictions the maximum number of series transistors is the number of input variables, n. With the estriction on the number of series transistors to R, the number of parallel transistors is less than or equal to 2R-1. Furthermore, the number of MOS cells and the number of levels of the MOS network are proportional to n and logRn, respectively. Since the designed network is similar to a complete tree, it would also be useful to process a series of combinations of input variable values.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Multilevel Network Design for Parity Functions with MOS Cells under Limitations on the Number of Series Transistors
T2 - IEICE TRANSACTIONS on transactions
SP - 791
EP - 798
AU - Yasuaki NISHITANI
AU - Kensuke SHIMIZU
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 8
JA - IEICE TRANSACTIONS on transactions
Y1 - August 1988
AB - A design method of multilevel logic networks, in single-rail input logic, with MOS cells for parity functions of n variables is presented. The parity functions x1x2xn in a two level network requires 2n-1+1 gates, whereas the number of NOR gates in a multilevel network for this function is proportional to n. Since MOS cells are playing a major role in LSI and can represent more complex functions than a NOR or a NAND gate, it is possible to obtain smaller networks with complex MOS cells than with NOR or NAND gates. However, if MOS cells become excessively complex, the propagation delay time of MOS cells is too large and the normal operation of the whole MOS network cannot be expected. The design procedure given in this paper is systematic and very easy to apply. In the beginning, the formulation of MOS cells and MOS networks has been presented. In this formulation, the number of series and parallel transistors and the number of MOS cells and levels can be defined and enumerated for MOS networks. Without the restrictions the maximum number of series transistors is the number of input variables, n. With the estriction on the number of series transistors to R, the number of parallel transistors is less than or equal to 2R-1. Furthermore, the number of MOS cells and the number of levels of the MOS network are proportional to n and logRn, respectively. Since the designed network is similar to a complete tree, it would also be useful to process a series of combinations of input variable values.
ER -
English
