2-GHz 8-Stage Synchronous Counter Using 400-Gate SST Bipolar Macrocell Array
Summary :
This letter presents the development of a high-speed 8-stage synchronous counter LSI which uses a 400-gate macrocell array. The LSI uses a sophisticated low-voltage-swing differential CML circuit technique and super-self-aligned Si-bipolar process technology (SST). The counter operates at up to 2 GHz with a chip power dissipation of 0.91 W.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E72-E No.8 pp.885-887
- Publication Date
- 1989/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Naoaki YAMANAKA, Masao SUZUKI, "2-GHz 8-Stage Synchronous Counter Using 400-Gate SST Bipolar Macrocell Array" in IEICE TRANSACTIONS on transactions,
vol. E72-E, no. 8, pp. 885-887, August 1989, doi: .
Abstract: This letter presents the development of a high-speed 8-stage synchronous counter LSI which uses a 400-gate macrocell array. The LSI uses a sophisticated low-voltage-swing differential CML circuit technique and super-self-aligned Si-bipolar process technology (SST). The counter operates at up to 2 GHz with a chip power dissipation of 0.91 W.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e72-e_8_885/_p
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@ARTICLE{e72-e_8_885,
author={Naoaki YAMANAKA, Masao SUZUKI, },
journal={IEICE TRANSACTIONS on transactions},
title={2-GHz 8-Stage Synchronous Counter Using 400-Gate SST Bipolar Macrocell Array},
year={1989},
volume={E72-E},
number={8},
pages={885-887},
abstract={This letter presents the development of a high-speed 8-stage synchronous counter LSI which uses a 400-gate macrocell array. The LSI uses a sophisticated low-voltage-swing differential CML circuit technique and super-self-aligned Si-bipolar process technology (SST). The counter operates at up to 2 GHz with a chip power dissipation of 0.91 W.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - 2-GHz 8-Stage Synchronous Counter Using 400-Gate SST Bipolar Macrocell Array
T2 - IEICE TRANSACTIONS on transactions
SP - 885
EP - 887
AU - Naoaki YAMANAKA
AU - Masao SUZUKI
PY - 1989
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E72-E
IS - 8
JA - IEICE TRANSACTIONS on transactions
Y1 - August 1989
AB - This letter presents the development of a high-speed 8-stage synchronous counter LSI which uses a 400-gate macrocell array. The LSI uses a sophisticated low-voltage-swing differential CML circuit technique and super-self-aligned Si-bipolar process technology (SST). The counter operates at up to 2 GHz with a chip power dissipation of 0.91 W.
ER -
English
