IEICE TRANSACTIONS on transactions
An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique
Summary :
An architecture for radix-2, decimation in frequency fast Fourier transform butterfly computation unit is proposed. It operates on 16 bit inputs and uses 'merged core' type of multipliers which reduce hardware components and hence promise smaller chip area. This reduction in area is achieved with negligible increase in computation delay.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.11 pp.1810-1812
- Publication Date
- 1990/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
- Category
- Signals, Circuits and Images
Authors
Keyword
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Farhad Fuad ISLAM, Hiroto YASUURA, Keikichi TAMARU, "An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 11, pp. 1810-1812, November 1990, doi: .
Abstract: An architecture for radix-2, decimation in frequency fast Fourier transform butterfly computation unit is proposed. It operates on 16 bit inputs and uses 'merged core' type of multipliers which reduce hardware components and hence promise smaller chip area. This reduction in area is achieved with negligible increase in computation delay.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_11_1810/_p
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@ARTICLE{e73-e_11_1810,
author={Farhad Fuad ISLAM, Hiroto YASUURA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on transactions},
title={An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique},
year={1990},
volume={E73-E},
number={11},
pages={1810-1812},
abstract={An architecture for radix-2, decimation in frequency fast Fourier transform butterfly computation unit is proposed. It operates on 16 bit inputs and uses 'merged core' type of multipliers which reduce hardware components and hence promise smaller chip area. This reduction in area is achieved with negligible increase in computation delay.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique
T2 - IEICE TRANSACTIONS on transactions
SP - 1810
EP - 1812
AU - Farhad Fuad ISLAM
AU - Hiroto YASUURA
AU - Keikichi TAMARU
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 11
JA - IEICE TRANSACTIONS on transactions
Y1 - November 1990
AB - An architecture for radix-2, decimation in frequency fast Fourier transform butterfly computation unit is proposed. It operates on 16 bit inputs and uses 'merged core' type of multipliers which reduce hardware components and hence promise smaller chip area. This reduction in area is achieved with negligible increase in computation delay.
ER -
English
