As technology moves at an annual area density increase rate of 80-120% and channel density moves beyond 3, micro-fluctuation of media recording performance and the homogeneity of media's recording capability become serious reliability concerns in future high density magnetic recording systems. Two concepts are proposed in this work for the characterization of the micro-recording performance fluctuation at high bit and channel densities: recording performance roughness analysis and dynamic magnetic roughness analysis. The recording performance roughness analysis is based on an in-situ measurement technique of the non-linear transition shift (NLTS). Relationship between the performance roughness and the roughness of dynamic magnetic parameters are studied. Results of experimental investigations indicate that the NLTS based performance roughness analysis can reveal more details on media's recording capability and the capability fluctuation--the macro and micro fluctuation of recording performance. The dynamic magnetic roughness analysis is read/write operation based and can be used to characterize the macro and micro fluctuation of media's dynamic magnetic properties. The parameters used for the analysis include media's dynamic coercivity and the dynamic coercive squareness. Here, "dynamic" refers to the dynamic performance measured at MHz frequency. The authors also noticed in their technology development process that further methodology development and confirmation are necessary for media's dynamic performance analysis. Therefore, the work also extends to the accuracy analysis of the playback amplitude based methods for the analysis of the dynamic coercive squareness and dynamic hysteresis loop. A method which is of smaller testing error is identified and reported in this work.

Maximizing the profit of datacenter networks (DCNs) demands to satisfy more flows' requirements simultaneously, but existing schemes always allocate resource based on single flow attribute, which cannot carry out accurate resource allocation and make many flows failed. In this letter, we propose Highest Priority Flow First (HPFF) to maximize DCN profit, which allocates resource for flows according to the priority. HPFF employs a utility function that considers multiple flow attributes, including flow size, deadline and demanded bandwidth, to calculate the priority for each flow. The experiments on the testbed show that HPFF can improve the network profit by 6.75%-19.7% and decrease the number of failed flow by 26.3%-83.3% compared with existing schemes under real DCN workloads.

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

Cloud computing, a novel distributed paradigm to provide powerful computing capabilities, is usually adopted by developers and researchers to execute complicated IoT applications such as complex workflows. In this scenario, it is fundamentally important to make an effective and efficient workflow application scheduling and execution by fully utilizing the advantages of the cloud (as virtualization and elastic services). However, in the current stage, there is relatively few research for workflow scheduling in cloud environment, where they usually just bring the traditional methods directly into cloud. Without considering the features of cloud, it may raise two kinds of problems: (1) The traditional methods mainly focus on static resource provision, which will cause the waste of resources; (2) They usually ignore the performance fluctuation of virtual machines on the physical machines, therefore it will lead to the estimation error of task execution time. To address these problems, a novel mechanism which can estimate the probability distribution of subtask execution time based on background VM load series over physical machines is proposed. An elastic performance fluctuations-aware stochastic scheduling algorithm is introduced in this paper. The experiments show that our proposed algorithm can outperform the existing algorithms in several metrics and can relieve the influence of performance fluctuations brought by the dynamic nature of cloud.

Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.