In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.

An approach to the enhancement of speech signals corrupted by additive colored noise is proposed and the system architecture to implement the proposed idea in real-time communication is introduced in this paper. A combination of a bandpass FIR filtering technique with wiener filtering is used to improve the SNR for speech signals. The average SNR improvement (between input and output SNR) is 22.48 dB. The additive noises are the sound from a turbo prop aircraft. The system, which shows excellent performance, is designed based on a 16 bits fixed point DSP (ADSP-2181) from Analog Devices. Experiment results demonstrate that the FIR filter leads to a significant gain in SNR, thus visibly improvement for the quality and the intelligibility of the speech.

This paper proposes a novel object tracking method via online boosting. The on-line boosting technique is combined with local features to treat tracking as a keypoint matching problem. First, We improve matching reliability by exploiting the statistical repeatability of local features. In addition, we propose 2D scale-rotation invariant quasi-keypoint matching to further improve matching efficiency. Benefiting from SURF feature's statistical repeatability and the complementary quasi-keypoint matching technique, we can easily find reliable matching pairs and thus perform accurate and stable tracking. Experimental results show that the proposed method achieves better performance compared with previously reported trackers.

In this paper, we address the issue of interference alignment (IA) in a two-cell network and consider both inter-cell and intra-cell interferences. For cell one, a linear processing scheme is proposed to align the inter-cell interference to the same signal dimension space of intra-cell interference. For cell two, we propose a distributed interference alignment scheme to manage the interference from the nearby cell. We assume that the relay works in an amplify-and-forward (AF) mode with a half-duplex and MIMO relaying. We show that the composite desired and interfering signals aggregated over two time slots can be aligned such that the interfering signal is eliminated completely by applying a linear filter at the receiver. The precoding matrix of the relay is optimized jointly with the precoding matrix of the base station (BS). The number of data streams is optimized jointly for every user terminal (UT). The degree of freedom (DoF) performance of the proposed scheme as well as the conventional cooperation scheme are derived for multiple antennas at both base stations, relay station and user terminals. Simulation results show that the proposed alignment scheme can achieve a better DoF performance.

Boolean matching is a fundamental problem in FPGA synthesis, but existing Boolean matchers are not scalable to complex PLBs (programmable logic blocks) and large circuits. This paper proposes a filter-based Boolean matching method, F-BM, which accelerates Boolean matching using lookup tables implemented by Bloom filters storing pre-calculated matching results. To show the effectiveness of the proposed F-BM, a post-mapping re-synthesis minimizing area which employs Boolean matching as the kernel has been implemented. Tested on a broad selection of benchmarks, the re-synthesizer using F-BM is 80X faster with 0.5% more area, compared with the one using a SAT-based Boolean matcher.

A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-$mu $m CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673,$mu $m$, imes ,$667,$mu $m with a core width of only 450,$mu $m. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8,V, a power of 200,mW is consumed and a single-ended swing of above 300,mV for each channel is achieved.