Model-based sensorless control of permanent magnet synchronous motor (PMSM) is promising for high-speed operation to estimate motor state, which is the speed and the position of the rotor, via electric signals of the stator, beside the inevitable fact that estimation accuracy is degraded by electromagnet interference (EMI) from switching devices of the converter. In this paper, the simulation system based on Luenberger observer and phase-locked loop (PLL) has been established, analyzing impacts of EMI on motor state estimations theoretically, exploring influences of EMI with different cutoff frequency, rated speeds, frequencies and amplitudes. The results show that Luenberger observer and PLL have strong immunity, which enable PMSM can still operate stably even under certain degrees of interference. EMI produces sideband harmonics that enlarge pulsation errors of speed and position estimations. Additionally, estimation errors are positively correlated with cutoff frequency of low-pass filter and the amplitude of EMI, and negatively correlated with rated speed of the motor and the frequency of EMI.  When the frequency is too high, its effects on motor state estimations are negligible. This work contributes to the comprehensive understanding of how EMI affects motor state estimations, which further enhances practical application of sensorless PMSM.

This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.

A current mode buck/boost DC-DC converter with automatic mode transition is presented in this paper. At heavy load, a control scheme adaptively changes operation mode between peak and valley current modes to achieve high efficiency, small output voltage ripple, and fast transient response. The switching loss is reduced by operating in pure modes, and the conduction loss is reduced by decreasing the average inductor current in transition modes. At light load, the equivalent switching frequency is decreased to reduce the switching loss. An automatic mode transition between heavy load PWM mode and light load PFM mode is achieved by introducing an average load current sensing method. The converter has been implemented with a standard 0.5,$mu$m CMOS process. The output voltage ripple is less than 10,mV in all modes, and the peak efficiency is 95%.

This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.