A large-scale packet-switch architecture for a tera bit/s system--which uses a combined-packet-distribution (CPD) method for a crossbar packet switch--was developed. This method eliminates the restriction on scheduling processing time by extending a switching data unit. The data unit is called a combined packet that consists of plural variable-length packets or their fragments. The combined packets are sequentially distributed among multiple crossbar switch planes and their sequence integrity is preserved. Distributive targets among the switch planes are selectable. As a result, when one or more switch planes are damaged, redundancy of the switch fabric is easily attained in a so-called "graceful degradation" manner. Moreover, this switch uses a novel algorithm called hierarchical priority scheduling. This algorithm enables fairness of scheduling by taking account of queuing state. The repetition required for priority scheduling is reduced by a novel hierarchical approach. The simulated performance of this algorithm shows that it performs better than the simple maximal matching method under both uniform and non-uniform traffic.

A novel 400-Gb/s (100-Gb/s4) physical-layer architecture for the next-generation Ethernet – using 100-Gb/s serial (optical single-wavelength) transmission – is proposed. As for the next-generation 400-Gb/s Ethernet, additional requirements from the market, such as power reduction and further miniaturization in addition to attaining even higher transmission speed, must be satisfied. To satisfy these requirements, a 100-Gb/s4 Ethernet physical-layer architecture is proposed. This architecture uses a 100-Gb/s serial (optical single-wavelength) transmission Ethernet and low-power technologies for a multi-lane transmission Ethernet. These technologies are implemented on a 100-Gb/s serial (optical single wavelength) transmission Ethernet using field-programmable gate arrays (FPGAs). Experimental evaluation of this implementation demonstrates the feasibility of low-power 400-Gb/s Ethernet.

The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 1210-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits10 lanes). One conveys forward error correction code ((132 b, 140 b) Hamming code), providing highly reliable (BER < 10-12) data transmission, and the other conveys parity data, enabling fault-lane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590 k gate circuit, which is small enough for implementation in a single LSI circuit.

A high-speed physical-layer architecture for next-generation higher-speed Ethernet for VSR and backplane applications was developed. VSR and backplane networks provide 100-Gb/s data transmission in "mega data centers" and blade servers, which have new and broad potential markets of LAN technologies. It supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for intra-building and intra-cabinet networks. Its links comprise ten 10-Gb/s high-speed serial lanes. Payload data are transmitted by ribbon fiber cables for very short reach and by copper channels for the backplane board. Ten lanes convey 320-bit data synchronously (32 bits10 lanes) and parity data of forward-error correction code (newly developed (544, 512) code FEC), providing highly reliable (BER<1E-22) data transmission with a burst-error correction with low latency (31.0 ns on the transmitter (Tx) side and 111.6 ns on the receiver (Rx) side). A 64B/66B code-sequence-based skew compensation mechanism, which provides low-latency compensation for the lane-to-lane skew (less than 51 ns), is used for parallel transmission. Testing this physical-layer architecture in an ASIC showed that it can provide 100-Gb/s data transmission with a 772-kgate circuit, which is small enough for implementation in a single LSI.