Signal Transmission and Coding Architecture for Next-Generation Ethernet

Hidehiro TOYODA; Hiroaki NISHI; Shinji NISHIMURA; Hisaaki KANAI; Katsuyoshi HARASAWA

Signal Transmission and Coding Architecture for Next-Generation Ethernet

Hidehiro TOYODA, Hiroaki NISHI, Shinji NISHIMURA, Hisaaki KANAI, Katsuyoshi HARASAWA

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The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.

Publication: IEICE TRANSACTIONS on Information Vol.E86-D No.11 pp.2317-2324

Publication Date: 2003/11/01

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Type of Manuscript: Special Section PAPER (Special Issue on New Technologies in the Internet and their Applications)

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Hidehiro TOYODA, Hiroaki NISHI, Shinji NISHIMURA, Hisaaki KANAI, Katsuyoshi HARASAWA, "Signal Transmission and Coding Architecture for Next-Generation Ethernet" in IEICE TRANSACTIONS on Information, vol. E86-D, no. 11, pp. 2317-2324, November 2003, doi: .
Abstract: The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_11_2317/_p

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@ARTICLE{e86-d_11_2317,
author={Hidehiro TOYODA, Hiroaki NISHI, Shinji NISHIMURA, Hisaaki KANAI, Katsuyoshi HARASAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Signal Transmission and Coding Architecture for Next-Generation Ethernet},
year={2003},
volume={E86-D},
number={11},
pages={2317-2324},
abstract={The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Signal Transmission and Coding Architecture for Next-Generation Ethernet
T2 - IEICE TRANSACTIONS on Information
SP - 2317
EP - 2324
AU - Hidehiro TOYODA
AU - Hiroaki NISHI
AU - Shinji NISHIMURA
AU - Hisaaki KANAI
AU - Katsuyoshi HARASAWA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2003
AB - The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.
ER -