A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.