Hetero-interface properties of SiO2/4H-SiC on (0001), (11-20), and (03-38) crystal orientations are presented. Epitaxial growth on new crystal orientations, (11-20) and (03-38), is described by comparing with the growth on (0001). Using thermal oxidation with wet oxygen, metal-oxide-SiC (MOS) structure was fabricated. From high-frequency capacitance-voltage characteristics measured at 300 K and 100 K, the interface properties were characterized semi-quantitatively. The interface state density was precisely determined using the conductance method for the MOS structure at 300 K. The new crystal orientations have the lower interface state density near the conduction band edge than (0001). From the characteristics of inversion-type planar MOSFETs, higher channel mobilities were obtained on (03-38) and (11-20) than on (0001). The cause of the difference in the channel mobility is speculated by the difference bond configuration of the three crystal orientations.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

Ultrahigh speed and low crosstalk four-channel receiver optoelectronic integrated circuit (OEIC) arrays comprising GaInAs pin PDs and A1InAs/GaInAs HEMTs have been successfully fabricated on an InP substrate. These arrays were designed to have good crosstalk characteristics which are the most critical issue in array devices. The resistive-load OEIC arrays exhibited high speed operation up to 5 Gb/s and low crosstalk of less than -38 dB between whole adjacent channels over entire frequency range below 4.0 GHz. The average sensitivity of resistive-load OEIC arrays was -18.5 dBm at 3 Gb/s for a bit-error-rate of 10-9 over four channels. Good uniformity of device characteristics was obtained over 2-inch InP wafer. These results suggest that receiver OEIC arrays are quite promising for the application to high-speed multi-channel optical interconnections.