16<cd0215f.gif>16 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks

Hiroshi YANO; Sosaku SAWADA; Kentaro DOGUCHI; Takashi KATO; Goro SASAKI

1616 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks

Hiroshi YANO, Sosaku SAWADA, Kentaro DOGUCHI, Takashi KATO, Goro SASAKI

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A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.5 pp.689-694

Publication Date: 1997/05/25

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Type of Manuscript: Special Section PAPER (Special Issue on Photonic Integrated Circuits)

Category: Optoelectronic Integrated Receivers

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Hiroshi YANO, Sosaku SAWADA, Kentaro DOGUCHI, Takashi KATO, Goro SASAKI, "1616 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 5, pp. 689-694, May 1997, doi: .
Abstract: A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_5_689/_p

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@ARTICLE{e80-c_5_689,
author={Hiroshi YANO, Sosaku SAWADA, Kentaro DOGUCHI, Takashi KATO, Goro SASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={1616 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks},
year={1997},
volume={E80-C},
number={5},
pages={689-694},
abstract={A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - 1616 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks
T2 - IEICE TRANSACTIONS on Electronics
SP - 689
EP - 694
AU - Hiroshi YANO
AU - Sosaku SAWADA
AU - Kentaro DOGUCHI
AU - Takashi KATO
AU - Goro SASAKI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1997
AB - A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.
ER -