To enhance fault tolerance ability of the feedforward neural networks (NNs for short) implemented in hardware, we discuss the learning algorithm that converges without adding extra neurons and a large amount of extra learning time and cycles. Our algorithm modified from the standard backpropagation algorithm (SBPA for short) limits synaptic weights of neurons in range during learning phase. The upper and lower bounds of the weights are calculated according to the average and standard deviation of them. Then our algorithm reupdates any weight beyond the calculated range to the upper or lower bound. Since the above enables us to decrease the standard deviation of the weights, it is useful in enhancing fault tolerance. We apply NNs trained with other algorithms and our one to a character recognition problem. It is shown that our one is superior to other ones in reliability, extra learning time and/or extra learning cycles. Besides we clarify that our algorithm never degrades the generalization ability of NNs although it coerces the weights within the calculated range.

If there is high uncertainty in the reliability of a system, it is required to know for which components to collect further failure data for making the uncertainty lower. This paper provides some solutions for such a requirement. First, the variance importance of a component is defined as a measure of component's contribution to the variance of the distribution of system unreliability. For reducing the system-variance efficiently, it would be suitable to collect failure data of comopnents having greater values of variance importance. Next, in the situation that we will perform life tests of components for making the variance of the distribution of system failure-rate smaller than its prior value, some problems for determinig both the number of samples to be tested and the test time for each component are formulated and solved.

This paper describes Kleenean coefficients that are a subset of Kleenean functions for use in representing multiple-valued logic functions. A conventional multiple-valued sum-of-products expression uses product terms that are the MIN of literals and constants. In this paper, a new sum-of-products expression is allowed to sum product terms that also include variables and complements of variables. Since the conventional sum-of-products expression is complete, so also is the augmented one. A minimization method of the new expression is described besed on the binary Quine-McCluskey algorithm. The result of computer simulation shows that a saving of the number of implicants used in minimal expressions by approximately 9% on the average can be obtained for some random functions. A result for some arithmetic functions shows that the minimal solutions of MOD radix SUM, MAX and MIN functions require much fewer implicants than those of the standard sum-of-products expressions. Thus, this paper clarifies that the new expression has an advantage to reduce the number of implicants in minimal sum-of-products expressions.

In this letter we propose an interpolation technique for low-quality fingerprint images for highly reliable feature extraction. To improve the feature extraction rate, we extract fingerprint features by referring to both the interpolated image obtained by using a directional Laplacian filter and the high-contrast image obtained by using histogram equalization. Experimental results show the applicability of our method.

This letter shows that an m-valued majority function is realized by m-1 two-valued threshold functions with common weight vector. A necessary and sufficient condition for an m-valued logical function to be a majority function is provided by using the concept of asummability.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

This paper is concerned with the synthesis of ternary logic function based on NOR-type polypheck. The system of fundamental operators consists of cyclic, inverse cyclic, logical sum and logical product. It is shown that any ternary logic function is represented by the logical sum of at most 2n-order terms. The simplification method in the binary logic system is extendedly applied to the ternary logic system. In synthesizing a ternary logic function based on NOR-type polypheck, the efficient tool, size of term, is newly-introduced. Size of term is defined by the total arithmetic sum of truth values of a term over all assignments of variable values. It has such characteristic that the decreased order of a term results in the increase of the size of the term. The utility of NOR-type polypheck is also discussed. The proposed method is applied to the ternary half-adder function as an example.

The reliability analysis of multi-state systems is needed for treating multi-modal failures, failure interdependency and degraded states. This paper defines some types of multi-state monotone systems from the positive relation between two states of components and presents their properties with emphasis on properties of Boolean structure functions with restricted 0-1 variables. Positive-directionally (or negative-directionally) monotone system is defined as the concept of monotone system wider than the former one, and its deterministic and probabilistic properties useful for the reliability analysis are given. Extended definitions of series, parallel and series-parallel systems are also given.

This paper presents a method for implementing the testing and realization of three-valued majority functions by using properties of 02-complete monotonicity which is an extended concept of complete monotonicity in binary logic. It is shown that reduced functions of three-valued majority functions are 02-completely monotonic, and all 7 or less variable three-valued logical functions satisfying the M(1) majority condition are three-valued majority functions if two-valued input three-valued output functions obtained by taking out only output values for 02-input vectors are 02-completely monotonic. For the realization of majority functions, m-variable inequalities are defined from 02-complete monotonicity. The weight vector is determined by solving weight inequalities derived from m-variable inequalities, and then thresholds are obtained. The overall algorithm of the method is given along with an example.

In this paper, the synthesis method of incompletely specified function based on NOR-type polypheck is presented. In synthesizing a function, the size of term is applied. The expanded simplification method in binary logic system is also applied.

In this paper, we discuss problems in design and fault masking of multiple-valued cellular arrays where basic cells having simple switch functions are arranged iteratively. The stuck-at faults of switch cells are assumed to be fault models. First, we introduce a universal single-level array and derive the ratio of the number of single faults whose influence can be masked to the total number of single faults. Next, we propose a universal two-level array that outputs correct values even if single faults occur in it and derive the ratio of the number of double faults whose influence can be masked compared to the total number of double faults. By evaluating the universal single-level array and the universal two-level array from the viewpoints of design and fault masking, we show that the latter is superior to the former. Finally, we compare our universal two-level array with formerly presented arrays in order to demonstrate the advantages of our universal two-level array.

Truncated sum (TSUM for short) is useful for MV-PLA's realization. This paper introduces a new class of multiple-valued logic functions that are expressed by truncated sum, differential product (DPRODUCT for short), NOT and variables, where TSUM (x, y)min (xy, p1) and DPRODUCT (x, y)max (xy(p1), 0) is newly defined as the product that is derived by applying De Morgan's laws to TSUM. We call the functions T-functios. First, this paper clarifies that a set of T-functions is not a lattice. It clarifies that Lukasiewicz implication can be expressed by TSUM and NOT. It guarantees that a set of p-valued T-functios is not complete but complete with constants. Next, the speculations of the number of T-functions for less than ten radixes are derived. For eleven or more radix p, a speculation of the number of p-valued T-functions is shown. Moreover, it compares the T-functions with B-functions. The B-functions have been defined as the functions expressed by MAX, MIN, NOT and variables. As a result, it shows that a set of T-functions includes a set of B-functions. Finally, an inclusion relation among these functional sets and normality condition is shown.

This paper proposes a repairable and diagnosable k-valued cellular array. We assume a single fault, i.e., either stuck-at-O fault or stuck-at-(k1) fault of switches occurs in the array. By building in a duplicate column iteratively, when a stuck-at-(k1) fault occurs in the array, the fault never influences the output of the array. That is, we can construct a fault-tolerant array for the stuck-at-(k1) fault. While, for the stuck-at-O fault, the diagnosing method is simple and easy because we don't have to diagnose the stuck-at-(k1) fault. Moreover, our array can be repaired easily for the fault. The comparison with other rectangular arrays shows that our array has advantages for the number of cells and the cost of the fault diagnosis.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

The purpose of this paper is to establish an access control system by using only fingerprint identification. In order to minimize the identification time, we propose a new fingerprint classification suitable for a personal computer, and the real machine by using the classification is introduced. Our classification is implemented by only cores which are one of the features on fingerprint pattern. Therefore, it classifies all fingerprints into one of 11 classes rapidly on a personal computer. In the machine, an input fingerprint is classified and compared with ones registered in the same class. If both the input fingerprint and the registered one match, the person is allowed entry to the restricted area. Simulation results show that 443 fingerprint patterns (45 persons) are classified completely and rapidly. And the machine is effective and useful as identifier for home and room security.